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AlisonSchofielddavejiang
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cxl/test: Define a CFMWS capable of a 3 way HB interleave
The CXL unit test cxl-xor-region.sh is skipping a 1+1+1 region interleave test case because the window is not defined. Additionally, upcoming expansion of 3 way HB interleave test cases (like 2+2+2) require the same window. Replace an unused CFMWS with a 3-way capable CFMWS in the set of CFMWS's loaded when interleave_arithmetic=1. Signed-off-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Tested-by: Li Zhijian <lizhijian@fujitsu.com> Link: https://patch.msgid.link/20250226221931.2352061-1-alison.schofield@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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tools/testing/cxl/test/cxl.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -155,7 +155,7 @@ static struct {
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} cfmws7;
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struct {
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struct acpi_cedt_cfmws cfmws;
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u32 target[4];
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u32 target[3];
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} cfmws8;
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struct {
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struct acpi_cedt_cxims cxims;
@@ -331,14 +331,14 @@ static struct {
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.length = sizeof(mock_cedt.cfmws8),
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},
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.interleave_arithmetic = ACPI_CEDT_CFMWS_ARITHMETIC_XOR,
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.interleave_ways = 2,
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.granularity = 0,
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.interleave_ways = 8,
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.granularity = 1,
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.restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
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ACPI_CEDT_CFMWS_RESTRICT_PMEM,
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.qtg_id = FAKE_QTG_ID,
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.window_size = SZ_256M * 16UL,
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.window_size = SZ_512M * 6UL,
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},
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.target = { 0, 1, 0, 1, },
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.target = { 0, 1, 2, },
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},
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.cxims0 = {
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.cxims = {

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