@@ -720,6 +720,39 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
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intel_pch_fifo_underrun_irq_handler (display , PIPE_B );
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}
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+ static u32 ivb_err_int_pipe_fault_mask (enum pipe pipe )
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+ {
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+ switch (pipe ) {
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+ case PIPE_A :
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+ return ERR_INT_SPRITE_A_FAULT |
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+ ERR_INT_PRIMARY_A_FAULT |
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+ ERR_INT_CURSOR_A_FAULT ;
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+ case PIPE_B :
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+ return ERR_INT_SPRITE_B_FAULT |
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+ ERR_INT_PRIMARY_B_FAULT |
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+ ERR_INT_CURSOR_B_FAULT ;
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+ case PIPE_C :
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+ return ERR_INT_SPRITE_C_FAULT |
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+ ERR_INT_PRIMARY_C_FAULT |
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+ ERR_INT_CURSOR_C_FAULT ;
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+ default :
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+ return 0 ;
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+ }
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+ }
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+
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+ static const struct pipe_fault_handler ivb_pipe_fault_handlers [] = {
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+ { .fault = ERR_INT_SPRITE_A_FAULT , .handle = handle_plane_fault , .plane_id = PLANE_SPRITE0 , },
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+ { .fault = ERR_INT_PRIMARY_A_FAULT , .handle = handle_plane_fault , .plane_id = PLANE_PRIMARY , },
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+ { .fault = ERR_INT_CURSOR_A_FAULT , .handle = handle_plane_fault , .plane_id = PLANE_CURSOR , },
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+ { .fault = ERR_INT_SPRITE_B_FAULT , .handle = handle_plane_fault , .plane_id = PLANE_SPRITE0 , },
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+ { .fault = ERR_INT_PRIMARY_B_FAULT , .handle = handle_plane_fault , .plane_id = PLANE_PRIMARY , },
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+ { .fault = ERR_INT_CURSOR_B_FAULT , .handle = handle_plane_fault , .plane_id = PLANE_CURSOR , },
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+ { .fault = ERR_INT_SPRITE_C_FAULT , .handle = handle_plane_fault , .plane_id = PLANE_SPRITE0 , },
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+ { .fault = ERR_INT_PRIMARY_C_FAULT , .handle = handle_plane_fault , .plane_id = PLANE_PRIMARY , },
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+ { .fault = ERR_INT_CURSOR_C_FAULT , .handle = handle_plane_fault , .plane_id = PLANE_CURSOR , },
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+ {}
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+ };
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+
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static void ivb_err_int_handler (struct drm_i915_private * dev_priv )
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{
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struct intel_display * display = & dev_priv -> display ;
@@ -729,7 +762,15 @@ static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
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if (err_int & ERR_INT_POISON )
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drm_err (& dev_priv -> drm , "Poison interrupt\n" );
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+ if (err_int & ERR_INT_INVALID_GTT_PTE )
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+ drm_err_ratelimited (display -> drm , "Invalid GTT PTE\n" );
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+
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+ if (err_int & ERR_INT_INVALID_PTE_DATA )
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+ drm_err_ratelimited (display -> drm , "Invalid PTE data\n" );
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+
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for_each_pipe (dev_priv , pipe ) {
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+ u32 fault_errors ;
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+
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if (err_int & ERR_INT_FIFO_UNDERRUN (pipe ))
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intel_cpu_fifo_underrun_irq_handler (display , pipe );
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@@ -739,6 +780,11 @@ static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
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else
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hsw_pipe_crc_irq_handler (dev_priv , pipe );
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}
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+
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+ fault_errors = err_int & ivb_err_int_pipe_fault_mask (pipe );
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+ if (fault_errors )
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+ intel_pipe_fault_irq_handler (display , ivb_pipe_fault_handlers ,
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+ pipe , fault_errors );
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}
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intel_de_write (display , GEN7_ERR_INT , err_int );
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