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Merge tag 'spi-fix-v6.5-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi fixes from Mark Brown: "A couple more small driver specific fixes for v6.5. The device mode for Cadence had been broken by some recent updates done for host mode and large transfers for multi-byte words on stm32 had been broken by an API update in what I think was a rebasing incident" * tag 'spi-fix-v6.5-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: spi-cadence: Fix data corruption issues in slave mode spi: stm32: fix accidential revert to byte-sized transfer splitting
2 parents b5cc383 + 627d05a commit 0de5ec4

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2 files changed

+15
-10
lines changed

2 files changed

+15
-10
lines changed

drivers/spi/spi-cadence.c

Lines changed: 12 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -317,12 +317,6 @@ static void cdns_spi_process_fifo(struct cdns_spi *xspi, int ntx, int nrx)
317317
xspi->rx_bytes -= nrx;
318318

319319
while (ntx || nrx) {
320-
/* When xspi in busy condition, bytes may send failed,
321-
* then spi control did't work thoroughly, add one byte delay
322-
*/
323-
if (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_TXFULL)
324-
udelay(10);
325-
326320
if (ntx) {
327321
if (xspi->txbuf)
328322
cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
@@ -392,6 +386,11 @@ static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
392386
if (xspi->tx_bytes) {
393387
cdns_spi_process_fifo(xspi, trans_cnt, trans_cnt);
394388
} else {
389+
/* Fixed delay due to controller limitation with
390+
* RX_NEMPTY incorrect status
391+
* Xilinx AR:65885 contains more details
392+
*/
393+
udelay(10);
395394
cdns_spi_process_fifo(xspi, 0, trans_cnt);
396395
cdns_spi_write(xspi, CDNS_SPI_IDR,
397396
CDNS_SPI_IXR_DEFAULT);
@@ -439,12 +438,18 @@ static int cdns_transfer_one(struct spi_controller *ctlr,
439438
cdns_spi_setup_transfer(spi, transfer);
440439
} else {
441440
/* Set TX empty threshold to half of FIFO depth
442-
* only if TX bytes are more than half FIFO depth.
441+
* only if TX bytes are more than FIFO depth.
443442
*/
444443
if (xspi->tx_bytes > xspi->tx_fifo_depth)
445444
cdns_spi_write(xspi, CDNS_SPI_THLD, xspi->tx_fifo_depth >> 1);
446445
}
447446

447+
/* When xspi in busy condition, bytes may send failed,
448+
* then spi control didn't work thoroughly, add one byte delay
449+
*/
450+
if (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_TXFULL)
451+
udelay(10);
452+
448453
cdns_spi_process_fifo(xspi, xspi->tx_fifo_depth, 0);
449454
spi_transfer_delay_exec(transfer);
450455

drivers/spi/spi-stm32.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1001,9 +1001,9 @@ static int stm32_spi_prepare_msg(struct spi_controller *ctrl,
10011001
if (spi->cfg->set_number_of_data) {
10021002
int ret;
10031003

1004-
ret = spi_split_transfers_maxsize(ctrl, msg,
1005-
STM32H7_SPI_TSIZE_MAX,
1006-
GFP_KERNEL | GFP_DMA);
1004+
ret = spi_split_transfers_maxwords(ctrl, msg,
1005+
STM32H7_SPI_TSIZE_MAX,
1006+
GFP_KERNEL | GFP_DMA);
10071007
if (ret)
10081008
return ret;
10091009
}

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