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Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 updates from Will Deacon: "Highlights include a major rework of our kPTI page-table rewriting code (which makes it both more maintainable and considerably faster in the cases where it is required) as well as significant changes to our early boot code to reduce the need for data cache maintenance and greatly simplify the KASLR relocation dance. Summary: - Remove unused generic cpuidle support (replaced by PSCI version) - Fix documentation describing the kernel virtual address space - Handling of some new CPU errata in Arm implementations - Rework of our exception table code in preparation for handling machine checks (i.e. RAS errors) more gracefully - Switch over to the generic implementation of ioremap() - Fix lockdep tracking in NMI context - Instrument our memory barrier macros for KCSAN - Rework of the kPTI G->nG page-table repainting so that the MMU remains enabled and the boot time is no longer slowed to a crawl for systems which require the late remapping - Enable support for direct swapping of 2MiB transparent huge-pages on systems without MTE - Fix handling of MTE tags with allocating new pages with HW KASAN - Expose the SMIDR register to userspace via sysfs - Continued rework of the stack unwinder, particularly improving the behaviour under KASAN - More repainting of our system register definitions to match the architectural terminology - Improvements to the layout of the vDSO objects - Support for allocating additional bits of HWCAP2 and exposing FEAT_EBF16 to userspace on CPUs that support it - Considerable rework and optimisation of our early boot code to reduce the need for cache maintenance and avoid jumping in and out of the kernel when handling relocation under KASLR - Support for disabling SVE and SME support on the kernel command-line - Support for the Hisilicon HNS3 PMU - Miscellanous cleanups, trivial updates and minor fixes" * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (136 commits) arm64: Delay initialisation of cpuinfo_arm64::reg_{zcr,smcr} arm64: fix KASAN_INLINE arm64/hwcap: Support FEAT_EBF16 arm64/cpufeature: Store elf_hwcaps as a bitmap rather than unsigned long arm64/hwcap: Document allocation of upper bits of AT_HWCAP arm64: enable THP_SWAP for arm64 arm64/mm: use GENMASK_ULL for TTBR_BADDR_MASK_52 arm64: errata: Remove AES hwcap for COMPAT tasks arm64: numa: Don't check node against MAX_NUMNODES drivers/perf: arm_spe: Fix consistency of SYS_PMSCR_EL1.CX perf: RISC-V: Add of_node_put() when breaking out of for_each_of_cpu_node() docs: perf: Include hns3-pmu.rst in toctree to fix 'htmldocs' WARNING arm64: kasan: Revert "arm64: mte: reset the page tag in page->flags" mm: kasan: Skip page unpoisoning only if __GFP_SKIP_KASAN_UNPOISON mm: kasan: Skip unpoisoning of user pages mm: kasan: Ensure the tags are visible before the tag in page->flags drivers/perf: hisi: add driver for HNS3 PMU drivers/perf: hisi: Add description for HNS3 PMU driver drivers/perf: riscv_pmu_sbi: perf format perf/arm-cci: Use the bitmap API to allocate bitmaps ...
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Documentation/ABI/testing/sysfs-devices-system-cpu

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@@ -493,12 +493,13 @@ What: /sys/devices/system/cpu/cpuX/regs/
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/sys/devices/system/cpu/cpuX/regs/identification/
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/sys/devices/system/cpu/cpuX/regs/identification/midr_el1
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/sys/devices/system/cpu/cpuX/regs/identification/revidr_el1
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/sys/devices/system/cpu/cpuX/regs/identification/smidr_el1
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Date: June 2016
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Contact: Linux ARM Kernel Mailing list <linux-arm-kernel@lists.infradead.org>
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Description: AArch64 CPU registers
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'identification' directory exposes the CPU ID registers for
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identifying model and revision of the CPU.
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identifying model and revision of the CPU and SMCU.
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What: /sys/devices/system/cpu/aarch32_el0
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Date: May 2021

Documentation/admin-guide/kernel-parameters.txt

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arm64.nomte [ARM64] Unconditionally disable Memory Tagging Extension
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support
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arm64.nosve [ARM64] Unconditionally disable Scalable Vector
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Extension support
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arm64.nosme [ARM64] Unconditionally disable Scalable Matrix
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Extension support
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ataflop= [HW,M68k]
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atarimouse= [HW,MOUSE] Atari Mouse
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improves system performance, but it may also
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expose users to several CPU vulnerabilities.
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Equivalent to: nopti [X86,PPC]
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kpti=0 [ARM64]
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if nokaslr then kpti=0 [ARM64]
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nospectre_v1 [X86,PPC]
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nobp=0 [S390]
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nospectre_v2 [X86,PPC,S390,ARM64]
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======================================
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HNS3 Performance Monitoring Unit (PMU)
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======================================
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HNS3(HiSilicon network system 3) Performance Monitoring Unit (PMU) is an
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End Point device to collect performance statistics of HiSilicon SoC NIC.
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On Hip09, each SICL(Super I/O cluster) has one PMU device.
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HNS3 PMU supports collection of performance statistics such as bandwidth,
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latency, packet rate and interrupt rate.
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Each HNS3 PMU supports 8 hardware events.
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HNS3 PMU driver
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===============
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The HNS3 PMU driver registers a perf PMU with the name of its sicl id.::
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/sys/devices/hns3_pmu_sicl_<sicl_id>
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PMU driver provides description of available events, filter modes, format,
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identifier and cpumask in sysfs.
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The "events" directory describes the event code of all supported events
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shown in perf list.
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The "filtermode" directory describes the supported filter modes of each
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event.
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The "format" directory describes all formats of the config (events) and
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config1 (filter options) fields of the perf_event_attr structure.
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The "identifier" file shows version of PMU hardware device.
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The "bdf_min" and "bdf_max" files show the supported bdf range of each
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pmu device.
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The "hw_clk_freq" file shows the hardware clock frequency of each pmu
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device.
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Example usage of checking event code and subevent code::
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$# cat /sys/devices/hns3_pmu_sicl_0/events/dly_tx_normal_to_mac_time
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config=0x00204
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$# cat /sys/devices/hns3_pmu_sicl_0/events/dly_tx_normal_to_mac_packet_num
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config=0x10204
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Each performance statistic has a pair of events to get two values to
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calculate real performance data in userspace.
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The bits 0~15 of config (here 0x0204) are the true hardware event code. If
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two events have same value of bits 0~15 of config, that means they are
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event pair. And the bit 16 of config indicates getting counter 0 or
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counter 1 of hardware event.
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After getting two values of event pair in usersapce, the formula of
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computation to calculate real performance data is:::
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counter 0 / counter 1
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Example usage of checking supported filter mode::
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$# cat /sys/devices/hns3_pmu_sicl_0/filtermode/bw_ssu_rpu_byte_num
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filter mode supported: global/port/port-tc/func/func-queue/
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Example usage of perf::
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$# perf list
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hns3_pmu_sicl_0/bw_ssu_rpu_byte_num/ [kernel PMU event]
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hns3_pmu_sicl_0/bw_ssu_rpu_time/ [kernel PMU event]
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------------------------------------------
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$# perf stat -g -e hns3_pmu_sicl_0/bw_ssu_rpu_byte_num,global=1/ -e hns3_pmu_sicl_0/bw_ssu_rpu_time,global=1/ -I 1000
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or
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$# perf stat -g -e hns3_pmu_sicl_0/config=0x00002,global=1/ -e hns3_pmu_sicl_0/config=0x10002,global=1/ -I 1000
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Filter modes
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--------------
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1. global mode
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PMU collect performance statistics for all HNS3 PCIe functions of IO DIE.
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Set the "global" filter option to 1 will enable this mode.
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Example usage of perf::
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$# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,global=1/ -I 1000
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2. port mode
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PMU collect performance statistic of one whole physical port. The port id
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is same as mac id. The "tc" filter option must be set to 0xF in this mode,
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here tc stands for traffic class.
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Example usage of perf::
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$# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,port=0,tc=0xF/ -I 1000
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3. port-tc mode
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PMU collect performance statistic of one tc of physical port. The port id
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is same as mac id. The "tc" filter option must be set to 0 ~ 7 in this
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mode.
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Example usage of perf::
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$# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,port=0,tc=0/ -I 1000
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4. func mode
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PMU collect performance statistic of one PF/VF. The function id is BDF of
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PF/VF, its conversion formula::
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func = (bus << 8) + (device << 3) + (function)
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for example:
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BDF func
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35:00.0 0x3500
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35:00.1 0x3501
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35:01.0 0x3508
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In this mode, the "queue" filter option must be set to 0xFFFF.
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Example usage of perf::
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$# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,bdf=0x3500,queue=0xFFFF/ -I 1000
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5. func-queue mode
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PMU collect performance statistic of one queue of PF/VF. The function id
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is BDF of PF/VF, the "queue" filter option must be set to the exact queue
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id of function.
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Example usage of perf::
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$# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,bdf=0x3500,queue=0/ -I 1000
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6. func-intr mode
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PMU collect performance statistic of one interrupt of PF/VF. The function
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id is BDF of PF/VF, the "intr" filter option must be set to the exact
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interrupt id of function.
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Example usage of perf::
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$# perf stat -a -e hns3_pmu_sicl_0/config=0x00301,bdf=0x3500,intr=0/ -I 1000

Documentation/admin-guide/perf/index.rst

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hisi-pmu
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hisi-pcie-pmu
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hns3-pmu
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imx-ddr
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qcom_l2_pmu
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qcom_l3_pmu

Documentation/arm64/elf_hwcaps.rst

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Functionality implied by ID_AA64ISAR2_EL1.WFXT == 0b0010.
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HWCAP2_EBF16
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Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0010.
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4. Unused AT_HWCAP bits
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-----------------------
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Documentation/arm64/memory.rst

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0000000000000000 0000ffffffffffff 256TB user
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ffff000000000000 ffff7fffffffffff 128TB kernel logical memory map
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[ffff600000000000 ffff7fffffffffff] 32TB [kasan shadow region]
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ffff800000000000 ffff800007ffffff 128MB bpf jit region
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ffff800008000000 ffff80000fffffff 128MB modules
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ffff800010000000 fffffbffefffffff 124TB vmalloc
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ffff800000000000 ffff800007ffffff 128MB modules
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ffff800008000000 fffffbffefffffff 124TB vmalloc
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fffffbfff0000000 fffffbfffdffffff 224MB fixed mappings (top down)
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fffffbfffe000000 fffffbfffe7fffff 8MB [guard region]
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fffffbfffe800000 fffffbffff7fffff 16MB PCI I/O space
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0000000000000000 000fffffffffffff 4PB user
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fff0000000000000 ffff7fffffffffff ~4PB kernel logical memory map
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[fffd800000000000 ffff7fffffffffff] 512TB [kasan shadow region]
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ffff800000000000 ffff800007ffffff 128MB bpf jit region
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ffff800008000000 ffff80000fffffff 128MB modules
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ffff800010000000 fffffbffefffffff 124TB vmalloc
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ffff800000000000 ffff800007ffffff 128MB modules
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ffff800008000000 fffffbffefffffff 124TB vmalloc
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fffffbfff0000000 fffffbfffdffffff 224MB fixed mappings (top down)
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fffffbfffe000000 fffffbfffe7fffff 8MB [guard region]
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fffffbfffe800000 fffffbffff7fffff 16MB PCI I/O space

Documentation/arm64/silicon-errata.rst

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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A57 | #1319537 | ARM64_ERRATUM_1319367 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A57 | #1742098 | ARM64_ERRATUM_1742098 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A72 | #853709 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A72 | #1319367 | ARM64_ERRATUM_1319367 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A72 | #1655431 | ARM64_ERRATUM_1742098 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A76 | #1188873,1418040| ARM64_ERRATUM_1418040 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2077057 | ARM64_ERRATUM_2077057 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2441009 | ARM64_ERRATUM_2441009 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 |

Documentation/features/vm/ioremap_prot/arch-support.txt

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| alpha: | TODO |
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| arc: | ok |
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| arm: | TODO |
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| arm64: | TODO |
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| arm64: | ok |
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| csky: | TODO |
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| hexagon: | TODO |
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| ia64: | TODO |

Documentation/memory-barriers.txt

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(*) dma_wmb();
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(*) dma_rmb();
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(*) dma_mb();
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These are for use with consistent memory to guarantee the ordering
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of writes or reads of shared memory accessible to both the CPU and a
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The dma_rmb() allows us guarantee the device has released ownership
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before we read the data from the descriptor, and the dma_wmb() allows
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us to guarantee the data is written to the descriptor before the device
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can see it now has ownership. Note that, when using writel(), a prior
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wmb() is not needed to guarantee that the cache coherent memory writes
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have completed before writing to the MMIO region. The cheaper
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writel_relaxed() does not provide this guarantee and must not be used
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here.
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can see it now has ownership. The dma_mb() implies both a dma_rmb() and
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a dma_wmb(). Note that, when using writel(), a prior wmb() is not needed
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to guarantee that the cache coherent memory writes have completed before
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writing to the MMIO region. The cheaper writel_relaxed() does not provide
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this guarantee and must not be used here.
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See the subsection "Kernel I/O barrier effects" for more information on
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relaxed I/O accessors and the Documentation/core-api/dma-api.rst file for

Documentation/virt/kvm/arm/hyp-abi.rst

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* ::
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x0 = HVC_VHE_RESTART (arm64 only)
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x0 = HVC_FINALISE_EL2 (arm64 only)
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Attempt to upgrade the kernel's exception level from EL1 to EL2 by enabling
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the VHE mode. This is conditioned by the CPU supporting VHE, the EL2 MMU
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being off, and VHE not being disabled by any other means (command line
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option, for example).
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Finish configuring EL2 depending on the command-line options,
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including an attempt to upgrade the kernel's exception level from
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EL1 to EL2 by enabling the VHE mode. This is conditioned by the CPU
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supporting VHE, the EL2 MMU being off, and VHE not being disabled by
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any other means (command line option, for example).
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Any other value of r0/x0 triggers a hypervisor-specific handling,
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which is not documented here.

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