phy: mediatek: mipi: mt8183: fix minimal supported frequency

mwalle · vinodkoul · commit 06f76e464ac8 · 2023-11-27T18:23:26.000+05:30
The lowest supported clock frequency of the PHY is 125MHz (see also mtk_mipi_tx_pll_enable()), but the clamping in .round_rate() has the wrong minimal value, which will make the .enable() op return -EINVAL on low frequencies. Fix the minimal clamping value. Fixes: efda51a ("drm/mediatek: add mipi_tx driver for mt8183") Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20231123110202.2025585-1-mwalle@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
@@ -100,7 +100,7 @@ static void mtk_mipi_tx_pll_disable(struct clk_hw *hw)
 static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 				       unsigned long *prate)
 {
-	return clamp_val(rate, 50000000, 1600000000);
+	return clamp_val(rate, 125000000, 1600000000);
 }
 
 static const struct clk_ops mtk_mipi_tx_pll_ops = {

Original file line number	Diff line number	Diff line change
`@@ -100,7 +100,7 @@ static void mtk_mipi_tx_pll_disable(struct clk_hw *hw)`
`100`	`100`	`static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,`
`101`	`101`	`unsigned long *prate)`
`102`	`102`	`{`
`103`		`- return clamp_val(rate, 50000000, 1600000000);`
	`103`	`+ return clamp_val(rate, 125000000, 1600000000);`
`104`	`104`	`}`
`105`	`105`
`106`	`106`	`static const struct clk_ops mtk_mipi_tx_pll_ops = {`