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phy: qcom-qmp-pcie: simplify clock handling
For some of existing PHYs for new binding we are going to change refgen to more correct "rchng". Rather than introducing additional code to handle legacy vs current bindings (and clock names), use devm_clk_bulk_get_optional(). Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230820142035.89903-6-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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‎drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

Lines changed: 7 additions & 71 deletions
Original file line numberDiff line numberDiff line change
@@ -2194,9 +2194,6 @@ struct qmp_phy_cfg {
21942194
const struct qmp_phy_init_tbl *serdes_4ln_tbl;
21952195
int serdes_4ln_num;
21962196

2197-
/* clock ids to be requested */
2198-
const char * const *clk_list;
2199-
int num_clks;
22002197
/* resets to be requested */
22012198
const char * const *reset_list;
22022199
int num_resets;
@@ -2275,24 +2272,8 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
22752272
}
22762273

22772274
/* list of clocks required by phy */
2278-
static const char * const ipq8074_pciephy_clk_l[] = {
2279-
"aux", "cfg_ahb",
2280-
};
2281-
2282-
static const char * const msm8996_phy_clk_l[] = {
2283-
"aux", "cfg_ahb", "ref",
2284-
};
2285-
2286-
static const char * const sc8280xp_pciephy_clk_l[] = {
2287-
"aux", "cfg_ahb", "ref", "rchng",
2288-
};
2289-
2290-
static const char * const sdm845_pciephy_clk_l[] = {
2291-
"aux", "cfg_ahb", "ref", "refgen",
2292-
};
2293-
2294-
static const char * const sa8775p_pciephy_clk_l[] = {
2295-
"aux", "cfg_ahb", "ref", "rchng", "phy_aux",
2275+
static const char * const qmp_pciephy_clk_l[] = {
2276+
"aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux",
22962277
};
22972278

22982279
/* list of regulators */
@@ -2367,8 +2348,6 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
23672348
.pcs = ipq8074_pcie_pcs_tbl,
23682349
.pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
23692350
},
2370-
.clk_list = ipq8074_pciephy_clk_l,
2371-
.num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
23722351
.reset_list = ipq8074_pciephy_reset_l,
23732352
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
23742353
.vreg_list = NULL,
@@ -2394,8 +2373,6 @@ static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
23942373
.pcs_misc = ipq8074_pcie_gen3_pcs_misc_tbl,
23952374
.pcs_misc_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_misc_tbl),
23962375
},
2397-
.clk_list = ipq8074_pciephy_clk_l,
2398-
.num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
23992376
.reset_list = ipq8074_pciephy_reset_l,
24002377
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
24012378
.vreg_list = NULL,
@@ -2423,8 +2400,6 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
24232400
.pcs_misc = ipq6018_pcie_pcs_misc_tbl,
24242401
.pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl),
24252402
},
2426-
.clk_list = ipq8074_pciephy_clk_l,
2427-
.num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
24282403
.reset_list = ipq8074_pciephy_reset_l,
24292404
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
24302405
.vreg_list = NULL,
@@ -2450,8 +2425,6 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
24502425
.pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl,
24512426
.pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
24522427
},
2453-
.clk_list = sdm845_pciephy_clk_l,
2454-
.num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
24552428
.reset_list = sdm845_pciephy_reset_l,
24562429
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
24572430
.vreg_list = qmp_phy_vreg_l,
@@ -2473,8 +2446,6 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
24732446
.pcs = sdm845_qhp_pcie_pcs_tbl,
24742447
.pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
24752448
},
2476-
.clk_list = sdm845_pciephy_clk_l,
2477-
.num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
24782449
.reset_list = sdm845_pciephy_reset_l,
24792450
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
24802451
.vreg_list = qmp_phy_vreg_l,
@@ -2510,8 +2481,6 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
25102481
.pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
25112482
.pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
25122483
},
2513-
.clk_list = sdm845_pciephy_clk_l,
2514-
.num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
25152484
.reset_list = sdm845_pciephy_reset_l,
25162485
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
25172486
.vreg_list = qmp_phy_vreg_l,
@@ -2547,8 +2516,6 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
25472516
.pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
25482517
.pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
25492518
},
2550-
.clk_list = sdm845_pciephy_clk_l,
2551-
.num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
25522519
.reset_list = sdm845_pciephy_reset_l,
25532520
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
25542521
.vreg_list = qmp_phy_vreg_l,
@@ -2572,8 +2539,6 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
25722539
.pcs = msm8998_pcie_pcs_tbl,
25732540
.pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
25742541
},
2575-
.clk_list = msm8996_phy_clk_l,
2576-
.num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
25772542
.reset_list = ipq8074_pciephy_reset_l,
25782543
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
25792544
.vreg_list = qmp_phy_vreg_l,
@@ -2601,8 +2566,6 @@ static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
26012566
.pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl,
26022567
.pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
26032568
},
2604-
.clk_list = sdm845_pciephy_clk_l,
2605-
.num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
26062569
.reset_list = sdm845_pciephy_reset_l,
26072570
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
26082571
.vreg_list = qmp_phy_vreg_l,
@@ -2636,8 +2599,6 @@ static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = {
26362599
.serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl),
26372600
},
26382601

2639-
.clk_list = sc8280xp_pciephy_clk_l,
2640-
.num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
26412602
.reset_list = sdm845_pciephy_reset_l,
26422603
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
26432604
.vreg_list = qmp_phy_vreg_l,
@@ -2671,8 +2632,6 @@ static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = {
26712632
.serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl),
26722633
},
26732634

2674-
.clk_list = sc8280xp_pciephy_clk_l,
2675-
.num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
26762635
.reset_list = sdm845_pciephy_reset_l,
26772636
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
26782637
.vreg_list = qmp_phy_vreg_l,
@@ -2709,8 +2668,6 @@ static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = {
27092668
.serdes_4ln_tbl = sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl,
27102669
.serdes_4ln_num = ARRAY_SIZE(sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl),
27112670

2712-
.clk_list = sc8280xp_pciephy_clk_l,
2713-
.num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
27142671
.reset_list = sdm845_pciephy_reset_l,
27152672
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
27162673
.vreg_list = qmp_phy_vreg_l,
@@ -2751,8 +2708,6 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
27512708
.pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_misc_tbl),
27522709
},
27532710

2754-
.clk_list = sdm845_pciephy_clk_l,
2755-
.num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
27562711
.reset_list = sdm845_pciephy_reset_l,
27572712
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
27582713
.vreg_list = qmp_phy_vreg_l,
@@ -2788,8 +2743,6 @@ static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = {
27882743
.rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl),
27892744
},
27902745

2791-
.clk_list = sc8280xp_pciephy_clk_l,
2792-
.num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
27932746
.reset_list = sdm845_pciephy_reset_l,
27942747
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
27952748
.vreg_list = qmp_phy_vreg_l,
@@ -2825,8 +2778,6 @@ static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = {
28252778
.pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl),
28262779
},
28272780

2828-
.clk_list = sc8280xp_pciephy_clk_l,
2829-
.num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
28302781
.reset_list = sdm845_pciephy_reset_l,
28312782
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
28322783
.vreg_list = qmp_phy_vreg_l,
@@ -2854,8 +2805,6 @@ static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = {
28542805
.pcs_misc = sdx65_qmp_pcie_pcs_misc_tbl,
28552806
.pcs_misc_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_misc_tbl),
28562807
},
2857-
.clk_list = sdm845_pciephy_clk_l,
2858-
.num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
28592808
.reset_list = sdm845_pciephy_reset_l,
28602809
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
28612810
.vreg_list = qmp_phy_vreg_l,
@@ -2889,8 +2838,6 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
28892838
.rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_rx_tbl),
28902839
},
28912840

2892-
.clk_list = sdm845_pciephy_clk_l,
2893-
.num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
28942841
.reset_list = sdm845_pciephy_reset_l,
28952842
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
28962843
.vreg_list = qmp_phy_vreg_l,
@@ -2931,8 +2878,6 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
29312878
.pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),
29322879
},
29332880

2934-
.clk_list = sdm845_pciephy_clk_l,
2935-
.num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
29362881
.reset_list = sdm845_pciephy_reset_l,
29372882
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
29382883
.vreg_list = qmp_phy_vreg_l,
@@ -2960,8 +2905,6 @@ static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = {
29602905
.pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl,
29612906
.pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl),
29622907
},
2963-
.clk_list = sc8280xp_pciephy_clk_l,
2964-
.num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
29652908
.reset_list = sdm845_pciephy_reset_l,
29662909
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
29672910
.vreg_list = qmp_phy_vreg_l,
@@ -2991,8 +2934,6 @@ static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = {
29912934
.ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl,
29922935
.ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl),
29932936
},
2994-
.clk_list = sc8280xp_pciephy_clk_l,
2995-
.num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
29962937
.reset_list = sdm845_pciephy_reset_l,
29972938
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
29982939
.vreg_list = sm8550_qmp_phy_vreg_l,
@@ -3028,8 +2969,6 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = {
30282969
.pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),
30292970
},
30302971

3031-
.clk_list = sa8775p_pciephy_clk_l,
3032-
.num_clks = ARRAY_SIZE(sa8775p_pciephy_clk_l),
30332972
.reset_list = sdm845_pciephy_reset_l,
30342973
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
30352974
.vreg_list = qmp_phy_vreg_l,
@@ -3064,8 +3003,6 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = {
30643003
.pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),
30653004
},
30663005

3067-
.clk_list = sa8775p_pciephy_clk_l,
3068-
.num_clks = ARRAY_SIZE(sa8775p_pciephy_clk_l),
30693006
.reset_list = sdm845_pciephy_reset_l,
30703007
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
30713008
.vreg_list = qmp_phy_vreg_l,
@@ -3188,7 +3125,7 @@ static int qmp_pcie_init(struct phy *phy)
31883125
goto err_assert_reset;
31893126
}
31903127

3191-
ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
3128+
ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);
31923129
if (ret)
31933130
goto err_assert_reset;
31943131

@@ -3209,7 +3146,7 @@ static int qmp_pcie_exit(struct phy *phy)
32093146

32103147
reset_control_bulk_assert(cfg->num_resets, qmp->resets);
32113148

3212-
clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
3149+
clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);
32133150

32143151
regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
32153152

@@ -3392,19 +3329,18 @@ static int qmp_pcie_reset_init(struct qmp_pcie *qmp)
33923329

33933330
static int qmp_pcie_clk_init(struct qmp_pcie *qmp)
33943331
{
3395-
const struct qmp_phy_cfg *cfg = qmp->cfg;
33963332
struct device *dev = qmp->dev;
3397-
int num = cfg->num_clks;
3333+
int num = ARRAY_SIZE(qmp_pciephy_clk_l);
33983334
int i;
33993335

34003336
qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
34013337
if (!qmp->clks)
34023338
return -ENOMEM;
34033339

34043340
for (i = 0; i < num; i++)
3405-
qmp->clks[i].id = cfg->clk_list[i];
3341+
qmp->clks[i].id = qmp_pciephy_clk_l[i];
34063342

3407-
return devm_clk_bulk_get(dev, num, qmp->clks);
3343+
return devm_clk_bulk_get_optional(dev, num, qmp->clks);
34083344
}
34093345

34103346
static void phy_clk_release_provider(void *res)

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