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Merge tag 'loongarch-kvm-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson into HEAD
LoongArch KVM changes for v6.13 1. Add iocsr and mmio bus simulation in kernel. 2. Add in-kernel interrupt controller emulation. 3. Add virt extension support for eiointc irqchip.
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.mailmap

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@@ -665,6 +665,7 @@ Tomeu Vizoso <tomeu@tomeuvizoso.net> <tomeu.vizoso@collabora.com>
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Thomas Graf <tgraf@suug.ch>
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Thomas Körper <socketcan@esd.eu> <thomas.koerper@esd.eu>
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Thomas Pedersen <twp@codeaurora.org>
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Thorsten Blum <thorsten.blum@linux.dev> <thorsten.blum@toblux.com>
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Tiezhu Yang <yangtiezhu@loongson.cn> <kernelpatch@126.com>
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Tingwei Zhang <quic_tingwei@quicinc.com> <tingwei@codeaurora.org>
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Tirupathi Reddy <quic_tirupath@quicinc.com> <tirupath@codeaurora.org>

CREDITS

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S: D-57250 Netphen
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S: Germany
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N: Florian Fainelli
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E: f.fainelli@gmail.com
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D: DSA
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N: Rik Faith
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E: faith@acm.org
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D: Future Domain TMC-16x0 SCSI driver (author)

Documentation/admin-guide/kernel-parameters.txt

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0: no polling (default)
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thp_anon= [KNL]
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Format: <size>,<size>[KMG]:<state>;<size>-<size>[KMG]:<state>
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Format: <size>[KMG],<size>[KMG]:<state>;<size>[KMG]-<size>[KMG]:<state>
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state is one of "always", "madvise", "never" or "inherit".
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Control the default behavior of the system with respect
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to anonymous transparent hugepages.

Documentation/admin-guide/mm/transhuge.rst

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@@ -303,7 +303,7 @@ control by passing the parameter ``transparent_hugepage=always`` or
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kernel command line.
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Alternatively, each supported anonymous THP size can be controlled by
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passing ``thp_anon=<size>,<size>[KMG]:<state>;<size>-<size>[KMG]:<state>``,
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passing ``thp_anon=<size>[KMG],<size>[KMG]:<state>;<size>[KMG]-<size>[KMG]:<state>``,
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where ``<size>`` is the THP size (must be a power of 2 of PAGE_SIZE and
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supported anonymous THP) and ``<state>`` is one of ``always``, ``madvise``,
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``never`` or ``inherit``.

Documentation/arch/loongarch/irq-chip-model.rst

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| Devices |
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+---------+
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Virtual Extended IRQ model
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==========================
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In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt
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go to CPUINTC directly, CPU UARTS interrupts go to PCH-PIC, while all other
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devices interrupts go to PCH-PIC/PCH-MSI and gathered by V-EIOINTC (Virtual
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Extended I/O Interrupt Controller), and then go to CPUINTC directly::
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+-----+ +-------------------+ +-------+
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| IPI |--> | CPUINTC(0-255vcpu)| <-- | Timer |
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+-----+ +-------------------+ +-------+
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^
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|
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+-----------+
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| V-EIOINTC |
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+-----------+
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^ ^
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| |
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+---------+ +---------+
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| PCH-PIC | | PCH-MSI |
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+---------+ +---------+
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^ ^ ^
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| | |
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+--------+ +---------+ +---------+
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| UARTs | | Devices | | Devices |
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+--------+ +---------+ +---------+
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Description
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-----------
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V-EIOINTC (Virtual Extended I/O Interrupt Controller) is an extension of
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EIOINTC, it only works in VM mode which runs in KVM hypervisor. Interrupts can
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be routed to up to four vCPUs via standard EIOINTC, however with V-EIOINTC
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interrupts can be routed to up to 256 virtual cpus.
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With standard EIOINTC, interrupt routing setting includes two parts: eight
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bits for CPU selection and four bits for CPU IP (Interrupt Pin) selection.
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For CPU selection there is four bits for EIOINTC node selection, four bits
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for EIOINTC CPU selection. Bitmap method is used for CPU selection and
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CPU IP selection, so interrupt can only route to CPU0 - CPU3 and IP0-IP3 in
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one EIOINTC node.
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With V-EIOINTC it supports to route more CPUs and CPU IP (Interrupt Pin),
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there are two newly added registers with V-EIOINTC.
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EXTIOI_VIRT_FEATURES
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--------------------
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This register is read-only register, which indicates supported features with
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V-EIOINTC. Feature EXTIOI_HAS_INT_ENCODE and EXTIOI_HAS_CPU_ENCODE is added.
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Feature EXTIOI_HAS_INT_ENCODE is part of standard EIOINTC. If it is 1, it
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indicates that CPU Interrupt Pin selection can be normal method rather than
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bitmap method, so interrupt can be routed to IP0 - IP15.
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Feature EXTIOI_HAS_CPU_ENCODE is entension of V-EIOINTC. If it is 1, it
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indicates that CPU selection can be normal method rather than bitmap method,
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so interrupt can be routed to CPU0 - CPU255.
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EXTIOI_VIRT_CONFIG
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------------------
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This register is read-write register, for compatibility intterupt routed uses
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the default method which is the same with standard EIOINTC. If the bit is set
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with 1, it indicated HW to use normal method rather than bitmap method.
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Advanced Extended IRQ model
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===========================
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Documentation/devicetree/bindings/firmware/arm,scmi.yaml

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atomic mode of operation, even if requested.
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default: 0
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max-rx-timeout-ms:
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arm,max-rx-timeout-ms:
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description:
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An optional time value, expressed in milliseconds, representing the
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transport maximum timeout value for the receive channel. The value should

Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml

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- gmii
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- rgmii
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- sgmii
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- 1000BaseX
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- 1000base-x
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xlnx,phy-type:
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description:

Documentation/netlink/specs/mptcp_pm.yaml

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doc: Get endpoint information
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attribute-set: attr
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dont-validate: [ strict ]
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flags: [ uns-admin-perm ]
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do: &get-addr-attrs
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request:
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attributes:

Documentation/networking/j1939.rst

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On the other hand, when using PDU1 format, the PS-field contains a so-called
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Destination Address, which is _not_ part of the PGN. When communicating a PGN
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from user space to kernel (or vice versa) and PDU2 format is used, the PS-field
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from user space to kernel (or vice versa) and PDU1 format is used, the PS-field
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of the PGN shall be set to zero. The Destination Address shall be set
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elsewhere.
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Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst

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| Devices |
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+---------+
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虚拟扩展IRQ模型
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===============
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在这种模型里面, IPI(Inter-Processor Interrupt) 和CPU本地时钟中断直接发送到CPUINTC,
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CPU串口 (UARTs) 中断发送到PCH-PIC, 而其他所有设备的中断则分别发送到所连接的PCH_PIC/
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PCH-MSI, 然后V-EIOINTC统一收集,再直接到达CPUINTC::
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+-----+ +-------------------+ +-------+
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| IPI |--> | CPUINTC(0-255vcpu)| <-- | Timer |
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+-----+ +-------------------+ +-------+
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^
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|
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+-----------+
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| V-EIOINTC |
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+-----------+
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^ ^
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| |
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+---------+ +---------+
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| PCH-PIC | | PCH-MSI |
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+---------+ +---------+
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^ ^ ^
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| | |
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+--------+ +---------+ +---------+
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| UARTs | | Devices | | Devices |
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+--------+ +---------+ +---------+
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V-EIOINTC 是EIOINTC的扩展, 仅工作在虚拟机模式下, 中断经EIOINTC最多可个路由到
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4个虚拟CPU. 但中断经V-EIOINTC最多可个路由到256个虚拟CPU.
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传统的EIOINTC中断控制器,中断路由分为两个部分:8比特用于控制路由到哪个CPU,
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4比特用于控制路由到特定CPU的哪个中断管脚。控制CPU路由的8比特前4比特用于控制
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路由到哪个EIOINTC节点,后4比特用于控制此节点哪个CPU。中断路由在选择CPU路由
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和CPU中断管脚路由时,使用bitmap编码方式而不是正常编码方式,所以对于一个
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EIOINTC中断控制器节点,中断只能路由到CPU0 - CPU3,中断管脚IP0-IP3。
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V-EIOINTC新增了两个寄存器,支持中断路由到更多CPU个和中断管脚。
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V-EIOINTC功能寄存器
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-------------------
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功能寄存器是只读寄存器,用于显示V-EIOINTC支持的特性,目前两个支持两个特性
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EXTIOI_HAS_INT_ENCODE 和 EXTIOI_HAS_CPU_ENCODE。
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特性EXTIOI_HAS_INT_ENCODE是传统EIOINTC中断控制器的一个特性,如果此比特为1,
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显示CPU中断管脚路由方式支持正常编码,而不是bitmap编码,所以中断可以路由到
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管脚IP0 - IP15。
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特性EXTIOI_HAS_CPU_ENCODE是V-EIOINTC新增特性,如果此比特为1,表示CPU路由
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方式支持正常编码,而不是bitmap编码,所以中断可以路由到CPU0 - CPU255。
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V-EIOINTC配置寄存器
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-------------------
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配置寄存器是可读写寄存器,为了兼容性考虑,如果不写此寄存器,中断路由采用
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和传统EIOINTC相同的路由设置。如果对应比特设置为1,表示采用正常路由方式而
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不是bitmap编码的路由方式。
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高级扩展IRQ模型
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===============
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