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anderssonandersson
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Merge branch '20250313110359.242491-1-quic_mmanikan@quicinc.com' into clk-for-6.15
Merge the IPQ9574 NSSCC binding through a topic branch, to allow them to also be merged and used in the DeviceTree source tree.
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‎Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Anusha Rao <quic_anusha@quicinc.com>
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description: |
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Qualcomm networking sub system clock control module provides the clocks,
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resets on IPQ9574
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See also::
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include/dt-bindings/clock/qcom,ipq9574-nsscc.h
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include/dt-bindings/reset/qcom,ipq9574-nsscc.h
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properties:
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compatible:
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const: qcom,ipq9574-nsscc
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clocks:
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items:
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- description: Board XO source
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- description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source
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- description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source
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- description: GCC GPLL0 OUT AUX clock source
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- description: Uniphy0 NSS Rx clock source
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- description: Uniphy0 NSS Tx clock source
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- description: Uniphy1 NSS Rx clock source
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- description: Uniphy1 NSS Tx clock source
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- description: Uniphy2 NSS Rx clock source
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- description: Uniphy2 NSS Tx clock source
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- description: GCC NSSCC clock source
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'#interconnect-cells':
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const: 1
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clock-names:
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items:
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- const: xo
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- const: nss_1200
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- const: ppe_353
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- const: gpll0_out
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- const: uniphy0_rx
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- const: uniphy0_tx
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- const: uniphy1_rx
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- const: uniphy1_tx
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- const: uniphy2_rx
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- const: uniphy2_tx
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- const: bus
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required:
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- compatible
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- clocks
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- clock-names
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
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#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
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clock-controller@39b00000 {
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compatible = "qcom,ipq9574-nsscc";
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reg = <0x39b00000 0x80000>;
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clocks = <&xo_board_clk>,
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<&cmn_pll NSS_1200MHZ_CLK>,
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<&cmn_pll PPE_353MHZ_CLK>,
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<&gcc GPLL0_OUT_AUX>,
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<&uniphy 0>,
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<&uniphy 1>,
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<&uniphy 2>,
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<&uniphy 3>,
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<&uniphy 4>,
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<&uniphy 5>,
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<&gcc GCC_NSSCC_CLK>;
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clock-names = "xo",
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"nss_1200",
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"ppe_353",
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"gpll0_out",
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"uniphy0_rx",
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"uniphy0_tx",
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"uniphy1_rx",
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"uniphy1_tx",
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"uniphy2_rx",
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"uniphy2_tx",
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"bus";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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...

‎include/dt-bindings/clock/qcom,ipq9574-gcc.h

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#define GCC_PCIE1_PIPE_CLK 211
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#define GCC_PCIE2_PIPE_CLK 212
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#define GCC_PCIE3_PIPE_CLK 213
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#define GPLL0_OUT_AUX 214
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#endif

‎include/dt-bindings/clock/qcom,ipq9574-nsscc.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023, 2025 The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H
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#define _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H
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#define NSS_CC_CE_APB_CLK 0
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#define NSS_CC_CE_AXI_CLK 1
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#define NSS_CC_CE_CLK_SRC 2
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#define NSS_CC_CFG_CLK_SRC 3
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#define NSS_CC_CLC_AXI_CLK 4
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#define NSS_CC_CLC_CLK_SRC 5
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#define NSS_CC_CRYPTO_CLK 6
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#define NSS_CC_CRYPTO_CLK_SRC 7
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#define NSS_CC_CRYPTO_PPE_CLK 8
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#define NSS_CC_HAQ_AHB_CLK 9
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#define NSS_CC_HAQ_AXI_CLK 10
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#define NSS_CC_HAQ_CLK_SRC 11
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#define NSS_CC_IMEM_AHB_CLK 12
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#define NSS_CC_IMEM_CLK_SRC 13
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#define NSS_CC_IMEM_QSB_CLK 14
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#define NSS_CC_INT_CFG_CLK_SRC 15
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#define NSS_CC_NSS_CSR_CLK 16
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#define NSS_CC_NSSNOC_CE_APB_CLK 17
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#define NSS_CC_NSSNOC_CE_AXI_CLK 18
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#define NSS_CC_NSSNOC_CLC_AXI_CLK 19
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#define NSS_CC_NSSNOC_CRYPTO_CLK 20
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#define NSS_CC_NSSNOC_HAQ_AHB_CLK 21
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#define NSS_CC_NSSNOC_HAQ_AXI_CLK 22
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#define NSS_CC_NSSNOC_IMEM_AHB_CLK 23
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#define NSS_CC_NSSNOC_IMEM_QSB_CLK 24
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#define NSS_CC_NSSNOC_NSS_CSR_CLK 25
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#define NSS_CC_NSSNOC_PPE_CFG_CLK 26
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#define NSS_CC_NSSNOC_PPE_CLK 27
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#define NSS_CC_NSSNOC_UBI32_AHB0_CLK 28
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#define NSS_CC_NSSNOC_UBI32_AXI0_CLK 29
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#define NSS_CC_NSSNOC_UBI32_INT0_AHB_CLK 30
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#define NSS_CC_NSSNOC_UBI32_NC_AXI0_1_CLK 31
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#define NSS_CC_NSSNOC_UBI32_NC_AXI0_CLK 32
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#define NSS_CC_PORT1_MAC_CLK 33
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#define NSS_CC_PORT1_RX_CLK 34
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#define NSS_CC_PORT1_RX_CLK_SRC 35
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#define NSS_CC_PORT1_RX_DIV_CLK_SRC 36
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#define NSS_CC_PORT1_TX_CLK 37
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#define NSS_CC_PORT1_TX_CLK_SRC 38
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#define NSS_CC_PORT1_TX_DIV_CLK_SRC 39
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#define NSS_CC_PORT2_MAC_CLK 40
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#define NSS_CC_PORT2_RX_CLK 41
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#define NSS_CC_PORT2_RX_CLK_SRC 42
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#define NSS_CC_PORT2_RX_DIV_CLK_SRC 43
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#define NSS_CC_PORT2_TX_CLK 44
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#define NSS_CC_PORT2_TX_CLK_SRC 45
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#define NSS_CC_PORT2_TX_DIV_CLK_SRC 46
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#define NSS_CC_PORT3_MAC_CLK 47
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#define NSS_CC_PORT3_RX_CLK 48
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#define NSS_CC_PORT3_RX_CLK_SRC 49
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#define NSS_CC_PORT3_RX_DIV_CLK_SRC 50
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#define NSS_CC_PORT3_TX_CLK 51
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#define NSS_CC_PORT3_TX_CLK_SRC 52
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#define NSS_CC_PORT3_TX_DIV_CLK_SRC 53
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#define NSS_CC_PORT4_MAC_CLK 54
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#define NSS_CC_PORT4_RX_CLK 55
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#define NSS_CC_PORT4_RX_CLK_SRC 56
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#define NSS_CC_PORT4_RX_DIV_CLK_SRC 57
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#define NSS_CC_PORT4_TX_CLK 58
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#define NSS_CC_PORT4_TX_CLK_SRC 59
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#define NSS_CC_PORT4_TX_DIV_CLK_SRC 60
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#define NSS_CC_PORT5_MAC_CLK 61
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#define NSS_CC_PORT5_RX_CLK 62
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#define NSS_CC_PORT5_RX_CLK_SRC 63
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#define NSS_CC_PORT5_RX_DIV_CLK_SRC 64
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#define NSS_CC_PORT5_TX_CLK 65
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#define NSS_CC_PORT5_TX_CLK_SRC 66
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#define NSS_CC_PORT5_TX_DIV_CLK_SRC 67
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#define NSS_CC_PORT6_MAC_CLK 68
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#define NSS_CC_PORT6_RX_CLK 69
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#define NSS_CC_PORT6_RX_CLK_SRC 70
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#define NSS_CC_PORT6_RX_DIV_CLK_SRC 71
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#define NSS_CC_PORT6_TX_CLK 72
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#define NSS_CC_PORT6_TX_CLK_SRC 73
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#define NSS_CC_PORT6_TX_DIV_CLK_SRC 74
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#define NSS_CC_PPE_CLK_SRC 75
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#define NSS_CC_PPE_EDMA_CFG_CLK 76
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#define NSS_CC_PPE_EDMA_CLK 77
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#define NSS_CC_PPE_SWITCH_BTQ_CLK 78
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#define NSS_CC_PPE_SWITCH_CFG_CLK 79
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#define NSS_CC_PPE_SWITCH_CLK 80
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#define NSS_CC_PPE_SWITCH_IPE_CLK 81
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#define NSS_CC_UBI0_CLK_SRC 82
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#define NSS_CC_UBI0_DIV_CLK_SRC 83
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#define NSS_CC_UBI1_CLK_SRC 84
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#define NSS_CC_UBI1_DIV_CLK_SRC 85
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#define NSS_CC_UBI2_CLK_SRC 86
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#define NSS_CC_UBI2_DIV_CLK_SRC 87
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#define NSS_CC_UBI32_AHB0_CLK 88
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#define NSS_CC_UBI32_AHB1_CLK 89
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#define NSS_CC_UBI32_AHB2_CLK 90
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#define NSS_CC_UBI32_AHB3_CLK 91
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#define NSS_CC_UBI32_AXI0_CLK 92
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#define NSS_CC_UBI32_AXI1_CLK 93
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#define NSS_CC_UBI32_AXI2_CLK 94
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#define NSS_CC_UBI32_AXI3_CLK 95
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#define NSS_CC_UBI32_CORE0_CLK 96
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#define NSS_CC_UBI32_CORE1_CLK 97
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#define NSS_CC_UBI32_CORE2_CLK 98
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#define NSS_CC_UBI32_CORE3_CLK 99
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#define NSS_CC_UBI32_INTR0_AHB_CLK 100
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#define NSS_CC_UBI32_INTR1_AHB_CLK 101
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#define NSS_CC_UBI32_INTR2_AHB_CLK 102
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#define NSS_CC_UBI32_INTR3_AHB_CLK 103
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#define NSS_CC_UBI32_NC_AXI0_CLK 104
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#define NSS_CC_UBI32_NC_AXI1_CLK 105
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#define NSS_CC_UBI32_NC_AXI2_CLK 106
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#define NSS_CC_UBI32_NC_AXI3_CLK 107
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#define NSS_CC_UBI32_UTCM0_CLK 108
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#define NSS_CC_UBI32_UTCM1_CLK 109
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#define NSS_CC_UBI32_UTCM2_CLK 110
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#define NSS_CC_UBI32_UTCM3_CLK 111
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#define NSS_CC_UBI3_CLK_SRC 112
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#define NSS_CC_UBI3_DIV_CLK_SRC 113
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#define NSS_CC_UBI_AXI_CLK_SRC 114
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#define NSS_CC_UBI_NC_AXI_BFDCD_CLK_SRC 115
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#define NSS_CC_UNIPHY_PORT1_RX_CLK 116
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#define NSS_CC_UNIPHY_PORT1_TX_CLK 117
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#define NSS_CC_UNIPHY_PORT2_RX_CLK 118
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#define NSS_CC_UNIPHY_PORT2_TX_CLK 119
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#define NSS_CC_UNIPHY_PORT3_RX_CLK 120
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#define NSS_CC_UNIPHY_PORT3_TX_CLK 121
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#define NSS_CC_UNIPHY_PORT4_RX_CLK 122
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#define NSS_CC_UNIPHY_PORT4_TX_CLK 123
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#define NSS_CC_UNIPHY_PORT5_RX_CLK 124
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#define NSS_CC_UNIPHY_PORT5_TX_CLK 125
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#define NSS_CC_UNIPHY_PORT6_RX_CLK 126
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#define NSS_CC_UNIPHY_PORT6_TX_CLK 127
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#define NSS_CC_XGMAC0_PTP_REF_CLK 128
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#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 129
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#define NSS_CC_XGMAC1_PTP_REF_CLK 130
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#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 131
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#define NSS_CC_XGMAC2_PTP_REF_CLK 132
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#define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC 133
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#define NSS_CC_XGMAC3_PTP_REF_CLK 134
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#define NSS_CC_XGMAC3_PTP_REF_DIV_CLK_SRC 135
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#define NSS_CC_XGMAC4_PTP_REF_CLK 136
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#define NSS_CC_XGMAC4_PTP_REF_DIV_CLK_SRC 137
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#define NSS_CC_XGMAC5_PTP_REF_CLK 138
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#define NSS_CC_XGMAC5_PTP_REF_DIV_CLK_SRC 139
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#define UBI32_PLL 140
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#define UBI32_PLL_MAIN 141
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#endif

‎include/dt-bindings/reset/qcom,ipq9574-nsscc.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023, 2025 The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H
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#define _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H
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#define EDMA_HW_RESET 0
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#define NSS_CC_CE_BCR 1
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#define NSS_CC_CLC_BCR 2
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#define NSS_CC_EIP197_BCR 3
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#define NSS_CC_HAQ_BCR 4
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#define NSS_CC_IMEM_BCR 5
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#define NSS_CC_MAC_BCR 6
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#define NSS_CC_PPE_BCR 7
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#define NSS_CC_UBI_BCR 8
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#define NSS_CC_UNIPHY_BCR 9
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#define UBI3_CLKRST_CLAMP_ENABLE 10
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#define UBI3_CORE_CLAMP_ENABLE 11
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#define UBI2_CLKRST_CLAMP_ENABLE 12
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#define UBI2_CORE_CLAMP_ENABLE 13
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#define UBI1_CLKRST_CLAMP_ENABLE 14
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#define UBI1_CORE_CLAMP_ENABLE 15
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#define UBI0_CLKRST_CLAMP_ENABLE 16
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#define UBI0_CORE_CLAMP_ENABLE 17
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#define NSSNOC_NSS_CSR_ARES 18
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#define NSS_CSR_ARES 19
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#define PPE_BTQ_ARES 20
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#define PPE_IPE_ARES 21
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#define PPE_ARES 22
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#define PPE_CFG_ARES 23
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#define PPE_EDMA_ARES 24
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#define PPE_EDMA_CFG_ARES 25
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#define CRY_PPE_ARES 26
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#define NSSNOC_PPE_ARES 27
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#define NSSNOC_PPE_CFG_ARES 28
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#define PORT1_MAC_ARES 29
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#define PORT2_MAC_ARES 30
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#define PORT3_MAC_ARES 31
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#define PORT4_MAC_ARES 32
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#define PORT5_MAC_ARES 33
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#define PORT6_MAC_ARES 34
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#define XGMAC0_PTP_REF_ARES 35
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#define XGMAC1_PTP_REF_ARES 36
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#define XGMAC2_PTP_REF_ARES 37
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#define XGMAC3_PTP_REF_ARES 38
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#define XGMAC4_PTP_REF_ARES 39
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#define XGMAC5_PTP_REF_ARES 40
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#define HAQ_AHB_ARES 41
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#define HAQ_AXI_ARES 42
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#define NSSNOC_HAQ_AHB_ARES 43
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#define NSSNOC_HAQ_AXI_ARES 44
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#define CE_APB_ARES 45
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#define CE_AXI_ARES 46
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#define NSSNOC_CE_APB_ARES 47
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#define NSSNOC_CE_AXI_ARES 48
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#define CRYPTO_ARES 49
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#define NSSNOC_CRYPTO_ARES 50
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#define NSSNOC_NC_AXI0_1_ARES 51
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#define UBI0_CORE_ARES 52
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#define UBI1_CORE_ARES 53
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#define UBI2_CORE_ARES 54
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#define UBI3_CORE_ARES 55
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#define NC_AXI0_ARES 56
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#define UTCM0_ARES 57
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#define NC_AXI1_ARES 58
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#define UTCM1_ARES 59
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#define NC_AXI2_ARES 60
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#define UTCM2_ARES 61
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#define NC_AXI3_ARES 62
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#define UTCM3_ARES 63
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#define NSSNOC_NC_AXI0_ARES 64
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#define AHB0_ARES 65
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#define INTR0_AHB_ARES 66
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#define AHB1_ARES 67
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#define INTR1_AHB_ARES 68
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#define AHB2_ARES 69
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#define INTR2_AHB_ARES 70
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#define AHB3_ARES 71
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#define INTR3_AHB_ARES 72
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#define NSSNOC_AHB0_ARES 73
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#define NSSNOC_INT0_AHB_ARES 74
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#define AXI0_ARES 75
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#define AXI1_ARES 76
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#define AXI2_ARES 77
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#define AXI3_ARES 78
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#define NSSNOC_AXI0_ARES 79
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#define IMEM_QSB_ARES 80
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#define NSSNOC_IMEM_QSB_ARES 81
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#define IMEM_AHB_ARES 82
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#define NSSNOC_IMEM_AHB_ARES 83
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#define UNIPHY_PORT1_RX_ARES 84
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#define UNIPHY_PORT1_TX_ARES 85
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#define UNIPHY_PORT2_RX_ARES 86
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#define UNIPHY_PORT2_TX_ARES 87
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#define UNIPHY_PORT3_RX_ARES 88
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#define UNIPHY_PORT3_TX_ARES 89
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#define UNIPHY_PORT4_RX_ARES 90
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#define UNIPHY_PORT4_TX_ARES 91
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#define UNIPHY_PORT5_RX_ARES 92
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#define UNIPHY_PORT5_TX_ARES 93
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#define UNIPHY_PORT6_RX_ARES 94
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#define UNIPHY_PORT6_TX_ARES 95
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#define PORT1_RX_ARES 96
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#define PORT1_TX_ARES 97
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#define PORT2_RX_ARES 98
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#define PORT2_TX_ARES 99
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#define PORT3_RX_ARES 100
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#define PORT3_TX_ARES 101
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#define PORT4_RX_ARES 102
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#define PORT4_TX_ARES 103
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#define PORT5_RX_ARES 104
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#define PORT5_TX_ARES 105
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#define PORT6_RX_ARES 106
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#define PORT6_TX_ARES 107
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#define PPE_FULL_RESET 108
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#define UNIPHY0_SOFT_RESET 109
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#define UNIPHY1_SOFT_RESET 110
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#define UNIPHY2_SOFT_RESET 111
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#define UNIPHY_PORT1_ARES 112
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#define UNIPHY_PORT2_ARES 113
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#define UNIPHY_PORT3_ARES 114
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#define UNIPHY_PORT4_ARES 115
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#define UNIPHY_PORT5_ARES 116
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#define UNIPHY_PORT6_ARES 117
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#define NSSPORT1_RESET 118
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#define NSSPORT2_RESET 119
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#define NSSPORT3_RESET 120
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#define NSSPORT4_RESET 121
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#define NSSPORT5_RESET 122
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#define NSSPORT6_RESET 123
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#endif

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