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[eddyb's version/leftovers] add #[spirv(typed_buffer)] for explicit SpirvType::InterfaceBlocks.
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2 files changed

+4
-4
lines changed

2 files changed

+4
-4
lines changed

crates/rustc_codegen_spirv/src/abi.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -500,8 +500,8 @@ impl<'tcx> ConvSpirvType<'tcx> for TyAndLayout<'tcx> {
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// perfectly, in every way that could potentially affect ABI.
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if self.fields.offset(i) == Size::ZERO
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&& field.size == self.size
503-
&& field.align == self.align
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&& field.backend_repr == self.backend_repr
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&& field.align.abi == self.align.abi
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&& field.backend_repr.eq_up_to_validity(&self.backend_repr)
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{
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return field.spirv_type(span, cx);
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}

crates/spirv-std/src/typed_buffer.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,7 @@ impl<T> Deref for TypedBuffer<[T]> {
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"%result = OpCompositeConstruct typeof*{result_slot} %inner_ptr %inner_len",
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"OpStore {result_slot} %result",
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buffer = in(reg) self,
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result_slot = in(reg) &mut result_slot,
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result_slot = in(reg) result_slot.as_mut_ptr(),
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}
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result_slot.assume_init()
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}
@@ -94,7 +94,7 @@ impl<T> DerefMut for TypedBuffer<[T]> {
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"%result = OpCompositeConstruct typeof*{result_slot} %inner_ptr %inner_len",
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"OpStore {result_slot} %result",
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buffer = in(reg) self,
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result_slot = in(reg) &mut result_slot,
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result_slot = in(reg) result_slot.as_mut_ptr(),
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}
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result_slot.assume_init()
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}

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