Skip to content

Commit ad89af3

Browse files
dalpilRahix
dalpil
authored and
Rahix
committed
Implements simple_pwm for atmega32u4
1 parent 96be570 commit ad89af3

File tree

1 file changed

+210
-1
lines changed

1 file changed

+210
-1
lines changed

‎mcu/atmega-hal/src/simple_pwm.rs

Lines changed: 210 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -579,4 +579,213 @@ avr_hal_generic::impl_simple_pwm! {
579579

580580
},
581581
}
582-
}
582+
}
583+
584+
#[cfg(any(feature = "atmega32u4"))]
585+
avr_hal_generic::impl_simple_pwm! {
586+
/// Use `TC0` for PWM (pins `PB7`, `PD0`)
587+
///
588+
/// # Example
589+
/// ```
590+
/// let mut timer0 = Timer0Pwm::new(dp.TC0, Prescaler::Prescale64);
591+
///
592+
/// let mut d11 = pins.d11.into_output().into_pwm(&mut timer0);
593+
/// let mut d3 = pins.d3.into_output().into_pwm(&mut timer0);
594+
///
595+
/// d11.set_duty(128);
596+
/// d11.enable();
597+
/// ```
598+
pub struct Timer0Pwm {
599+
timer: crate::pac::TC0,
600+
init: |tim, prescaler| {
601+
tim.tccr0a.modify(|_r, w| w.wgm0().pwm_fast());
602+
tim.tccr0b.modify(|_r, w| match prescaler {
603+
Prescaler::Direct => w.cs0().direct(),
604+
Prescaler::Prescale8 => w.cs0().prescale_8(),
605+
Prescaler::Prescale64 => w.cs0().prescale_64(),
606+
Prescaler::Prescale256 => w.cs0().prescale_256(),
607+
Prescaler::Prescale1024 => w.cs0().prescale_1024(),
608+
});
609+
},
610+
pins: {
611+
PB7: {
612+
ocr: ocr0a,
613+
into_pwm: |tim| if enable {
614+
tim.tccr0a.modify(|_r, w| w.com0a().match_clear());
615+
} else {
616+
tim.tccr0a.modify(|_r, w| w.com0a().disconnected());
617+
},
618+
},
619+
620+
PD0: {
621+
ocr: ocr0b,
622+
into_pwm: |tim| if enable {
623+
tim.tccr0a.modify(|_r, w| w.com0b().match_clear());
624+
} else {
625+
tim.tccr0a.modify(|_r, w| w.com0b().disconnected());
626+
},
627+
},
628+
},
629+
}
630+
}
631+
632+
#[cfg(any(feature = "atmega32u4"))]
633+
avr_hal_generic::impl_simple_pwm! {
634+
/// Use `TC1` for PWM (pins `PB5`, `PB6`, `PB7`)
635+
///
636+
/// # Example
637+
/// ```
638+
/// let mut timer1 = Timer1Pwm::new(dp.TC1, Prescaler::Prescale64);
639+
///
640+
/// let mut d9 = pins.d9.into_output().into_pwm(&mut timer1);
641+
/// let mut d10 = pins.d10.into_output().into_pwm(&mut timer1);
642+
/// let mut d11 = pins.d11.into_output().into_pwm(&mut timer1);
643+
///
644+
/// d9.set_duty(128);
645+
/// d9.enable();
646+
/// ```
647+
pub struct Timer1Pwm {
648+
timer: crate::pac::TC1,
649+
init: |tim, prescaler| {
650+
tim.tccr1a.modify(|_r, w| w.wgm1().bits(0b01));
651+
tim.tccr1b.modify(|_r, w| w.wgm1().bits(0b01));
652+
653+
tim.tccr1b.modify(|_r, w| match prescaler {
654+
Prescaler::Direct => w.cs1().direct(),
655+
Prescaler::Prescale8 => w.cs1().prescale_8(),
656+
Prescaler::Prescale64 => w.cs1().prescale_64(),
657+
Prescaler::Prescale256 => w.cs1().prescale_256(),
658+
Prescaler::Prescale1024 => w.cs1().prescale_1024(),
659+
});
660+
},
661+
pins: {
662+
PB5: {
663+
ocr: ocr1a,
664+
into_pwm: |tim| if enable {
665+
tim.tccr1a.modify(|_r, w| w.com1a().match_clear());
666+
} else {
667+
tim.tccr1a.modify(|_r, w| w.com1a().disconnected());
668+
},
669+
},
670+
671+
PB6: {
672+
ocr: ocr1b,
673+
into_pwm: |tim| if enable {
674+
tim.tccr1a.modify(|_r, w| w.com1b().match_clear());
675+
} else {
676+
tim.tccr1a.modify(|_r, w| w.com1b().disconnected());
677+
},
678+
},
679+
680+
PB7: {
681+
ocr: ocr1c,
682+
into_pwm: |tim| if enable {
683+
tim.tccr1a.modify(|_r, w| w.com1c().match_clear());
684+
} else {
685+
tim.tccr1a.modify(|_r, w| w.com1c().disconnected());
686+
},
687+
},
688+
},
689+
}
690+
}
691+
692+
#[cfg(any(feature = "atmega32u4"))]
693+
avr_hal_generic::impl_simple_pwm! {
694+
/// Use `TC3` for PWM (pins `PC6`)
695+
///
696+
/// # Example
697+
/// ```
698+
/// let mut timer3 = Timer3Pwm::new(dp.TC3, Prescaler::Prescale64);
699+
///
700+
/// let mut d5 = pins.d5.into_output().into_pwm(&mut timer3);
701+
///
702+
/// d5.set_duty(128);
703+
/// d5.enable();
704+
/// ```
705+
pub struct Timer3Pwm {
706+
timer: crate::pac::TC3,
707+
init: |tim, prescaler| {
708+
tim.tccr3a.modify(|_r, w| w.wgm3().bits(0b01));
709+
tim.tccr3b.modify(|_r, w| w.wgm3().bits(0b01));
710+
711+
tim.tccr3b.modify(|_r, w| match prescaler {
712+
Prescaler::Direct => w.cs3().direct(),
713+
Prescaler::Prescale8 => w.cs3().prescale_8(),
714+
Prescaler::Prescale64 => w.cs3().prescale_64(),
715+
Prescaler::Prescale256 => w.cs3().prescale_256(),
716+
Prescaler::Prescale1024 => w.cs3().prescale_1024(),
717+
});
718+
},
719+
pins: {
720+
PC6: {
721+
ocr: ocr3a,
722+
into_pwm: |tim| if enable {
723+
tim.tccr3a.modify(|_r, w| w.com3a().match_clear());
724+
} else {
725+
tim.tccr3a.modify(|_r, w| w.com3a().disconnected());
726+
},
727+
},
728+
},
729+
}
730+
}
731+
732+
#[cfg(any(feature = "atmega32u4"))]
733+
avr_hal_generic::impl_simple_pwm! {
734+
/// Use `TC4` for PWM (pins `PB6`, `PC7`, `PD7`)
735+
///
736+
/// # Example
737+
/// ```
738+
/// let mut timer4 = Timer4Pwm::new(dp.TC4, Prescaler::Prescale64);
739+
///
740+
/// let mut d6 = pins.d6.into_output().into_pwm(&mut timer4);
741+
/// let mut d10 = pins.d10.into_output().into_pwm(&mut timer4);
742+
/// let mut d13 = pins.d13.into_output().into_pwm(&mut timer4);
743+
///
744+
/// d6.set_duty(128);
745+
/// d6.enable();
746+
/// ```
747+
pub struct Timer4Pwm {
748+
timer: crate::pac::TC4,
749+
init: |tim, prescaler| {
750+
tim.tccr4a.modify(|_r, w| w.pwm4a().set_bit());
751+
tim.tccr4a.modify(|_r, w| w.pwm4b().set_bit());
752+
tim.tccr4c.modify(|_r, w| w.pwm4d().set_bit());
753+
754+
tim.tccr4b.modify(|_r, w| match prescaler {
755+
Prescaler::Direct => w.cs4().direct(),
756+
Prescaler::Prescale8 => w.cs4().prescale_8(),
757+
Prescaler::Prescale64 => w.cs4().prescale_64(),
758+
Prescaler::Prescale256 => w.cs4().prescale_256(),
759+
Prescaler::Prescale1024 => w.cs4().prescale_1024(),
760+
});
761+
},
762+
pins: {
763+
PB6: {
764+
ocr: ocr4b,
765+
into_pwm: |tim| if enable {
766+
tim.tccr4a.modify(|_r, w| w.com4b().match_clear());
767+
} else {
768+
tim.tccr4a.modify(|_r, w| w.com4b().disconnected());
769+
},
770+
},
771+
772+
PC7: {
773+
ocr: ocr4a,
774+
into_pwm: |tim| if enable {
775+
tim.tccr4a.modify(|_r, w| w.com4a().match_clear());
776+
} else {
777+
tim.tccr4a.modify(|_r, w| w.com4a().disconnected());
778+
},
779+
},
780+
781+
PD7: {
782+
ocr: ocr4d,
783+
into_pwm: |tim| if enable {
784+
tim.tccr4c.modify(|_r, w| w.com4d().match_clear());
785+
} else {
786+
tim.tccr4c.modify(|_r, w| w.com4d().disconnected());
787+
},
788+
},
789+
},
790+
}
791+
}

0 commit comments

Comments
 (0)