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attiny-hal: Add ATtiny167 and ADC support for all chips
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‎.github/workflows/ci.yml

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@@ -62,6 +62,10 @@ jobs:
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name: attiny88
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spec: attiny88
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crate: attiny-hal
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- type: mcu
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name: attiny167
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spec: attiny167
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crate: attiny-hal
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runs-on: ubuntu-latest
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steps:
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- name: Checkout code

‎avr-specs/avr-attiny167.json

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@@ -0,0 +1,27 @@
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{
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"arch": "avr",
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"atomic-cas": false,
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"cpu": "attiny167",
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"data-layout": "e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8",
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"eh-frame-header": false,
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"exe-suffix": ".elf",
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"executables": true,
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"late-link-args": {
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"gcc": [
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"-lgcc"
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]
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},
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"linker": "avr-gcc",
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"linker-is-gnu": true,
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"llvm-target": "avr-unknown-unknown",
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"max-atomic-width": 8,
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"no-default-libraries": false,
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"pre-link-args": {
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"gcc": [
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"-mmcu=attiny167",
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"-Wl,--as-needed"
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]
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},
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"target-c-int-width": "16",
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"target-pointer-width": "16"
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}

‎avr-specs/sync-from-upstream.py

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@@ -28,6 +28,9 @@
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"attiny88": {
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"cpu": "attiny88",
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},
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"attiny167": {
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"cpu": "attiny167",
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},
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}
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COMMON = {

‎mcu/attiny-hal/Cargo.toml

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@@ -10,6 +10,7 @@ device-selected = []
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attiny84 = ["avr-device/attiny84", "device-selected"]
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attiny85 = ["avr-device/attiny85", "device-selected"]
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attiny88 = ["avr-device/attiny88", "device-selected"]
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attiny167 = ["avr-device/attiny167", "device-selected"]
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# Allow certain downstream crates to overwrite the device selection error by themselves.
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disable-device-selection-error = []

‎mcu/attiny-hal/src/adc.rs

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//! Analog-to-Digital Converter
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use crate::port;
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pub use avr_hal_generic::adc::{AdcChannel, AdcOps, ClockDivider};
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/// Select the voltage reference for the ADC peripheral
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///
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/// The internal voltage reference options may not be used if an external reference voltage is
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/// being applied to the AREF pin.
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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#[repr(u8)]
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pub enum ReferenceVoltage {
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/// Voltage applied to AREF pin.
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#[cfg(any(
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feature = "attiny85",
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feature = "attiny167",
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))]
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Aref,
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/// Default reference voltage (default).
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AVcc,
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/// Internal 1.1V reference.
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Internal1_1,
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/// Internal 2.56V reference.
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#[cfg(any(
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feature = "attiny85",
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feature = "attiny167",
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))]
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Internal2_56,
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}
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impl Default for ReferenceVoltage {
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fn default() -> Self {
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Self::AVcc
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}
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}
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/// Configuration for the ADC peripheral.
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#[derive(Default, Debug, Clone, Copy, PartialEq, Eq)]
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pub struct AdcSettings {
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pub clock_divider: ClockDivider,
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pub ref_voltage: ReferenceVoltage,
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}
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/// Check the [`avr_hal_generic::adc::Adc`] documentation.
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pub type Adc<CLOCK> = avr_hal_generic::adc::Adc<crate::Attiny, crate::pac::ADC, CLOCK>;
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/// Check the [`avr_hal_generic::adc::Channel`] documentation.
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pub type Channel = avr_hal_generic::adc::Channel<crate::Attiny, crate::pac::ADC>;
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/// Additional channels
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///
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/// Some channels are not directly connected to pins. This module provides types which can be used
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/// to access them.
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///
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/// # Example
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/// ```
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/// let dp = atmega_hal::Peripherals::take().unwrap();
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/// let mut adc = atmega_hal::Adc::new(dp.ADC, Default::default());
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///
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/// let value = adc.read_blocking(&channel::Vbg);
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/// ```
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pub mod channel {
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#[cfg(feature = "attiny167")]
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pub struct AVcc_4;
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pub struct Vbg;
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pub struct Gnd;
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pub struct Temperature;
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}
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fn apply_clock(peripheral: &crate::pac::ADC, settings: AdcSettings) {
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peripheral.adcsra.write(|w| {
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w.aden().set_bit();
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match settings.clock_divider {
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ClockDivider::Factor2 => w.adps().prescaler_2(),
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ClockDivider::Factor4 => w.adps().prescaler_4(),
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ClockDivider::Factor8 => w.adps().prescaler_8(),
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ClockDivider::Factor16 => w.adps().prescaler_16(),
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ClockDivider::Factor32 => w.adps().prescaler_32(),
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ClockDivider::Factor64 => w.adps().prescaler_64(),
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ClockDivider::Factor128 => w.adps().prescaler_128(),
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}
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});
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}
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#[cfg(feature = "attiny85")]
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avr_hal_generic::impl_adc! {
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hal: crate::Attiny,
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peripheral: crate::pac::ADC,
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settings: AdcSettings,
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apply_settings: |peripheral, settings| {
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apply_clock(peripheral, settings);
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peripheral.admux.write(|w| match settings.ref_voltage {
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ReferenceVoltage::Aref => w.refs().aref(),
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ReferenceVoltage::AVcc => w.refs().vcc(),
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ReferenceVoltage::Internal1_1 => w.refs().internal().refs2().clear_bit(),
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ReferenceVoltage::Internal2_56 => w.refs().internal().refs2().set_bit(),
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});
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},
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channel_id: crate::pac::adc::admux::MUX_A,
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set_channel: |peripheral, id| {
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peripheral.admux.modify(|_, w| w.mux().variant(id));
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},
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pins: {
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port::PB5: (crate::pac::adc::admux::MUX_A::ADC0, didr0::adc0d),
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port::PB2: (crate::pac::adc::admux::MUX_A::ADC1, didr0::adc1d),
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port::PB4: (crate::pac::adc::admux::MUX_A::ADC2, didr0::adc2d),
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port::PB3: (crate::pac::adc::admux::MUX_A::ADC3, didr0::adc3d),
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},
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channels: {
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channel::Vbg: crate::pac::adc::admux::MUX_A::ADC_VBG,
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channel::Gnd: crate::pac::adc::admux::MUX_A::ADC_GND,
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channel::Temperature: crate::pac::adc::admux::MUX_A::TEMPSENS,
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},
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}
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#[cfg(feature = "attiny88")]
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avr_hal_generic::impl_adc! {
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hal: crate::Attiny,
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peripheral: crate::pac::ADC,
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settings: AdcSettings,
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apply_settings: |peripheral, settings| {
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apply_clock(peripheral, settings);
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peripheral.admux.write(|w| match settings.ref_voltage {
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ReferenceVoltage::AVcc => w.refs0().avcc(),
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ReferenceVoltage::Internal1_1 => w.refs0().internal(),
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});
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},
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channel_id: crate::pac::adc::admux::MUX_A,
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set_channel: |peripheral, id| {
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peripheral.admux.modify(|_, w| w.mux().variant(id));
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},
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pins: {
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port::PC0: (crate::pac::adc::admux::MUX_A::ADC0, didr0::adc0d),
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port::PC1: (crate::pac::adc::admux::MUX_A::ADC1, didr0::adc1d),
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port::PC2: (crate::pac::adc::admux::MUX_A::ADC2, didr0::adc2d),
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port::PC3: (crate::pac::adc::admux::MUX_A::ADC3, didr0::adc3d),
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port::PC4: (crate::pac::adc::admux::MUX_A::ADC4, didr0::adc4d),
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port::PC5: (crate::pac::adc::admux::MUX_A::ADC5, didr0::adc5d),
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port::PA0: (crate::pac::adc::admux::MUX_A::ADC6, didr0::adc6d),
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port::PA1: (crate::pac::adc::admux::MUX_A::ADC7, didr0::adc7d),
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},
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channels: {
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channel::Vbg: crate::pac::adc::admux::MUX_A::ADC_VBG,
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channel::Gnd: crate::pac::adc::admux::MUX_A::ADC_GND,
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channel::Temperature: crate::pac::adc::admux::MUX_A::TEMPSENS,
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},
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}
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#[cfg(feature = "attiny167")]
153+
avr_hal_generic::impl_adc! {
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hal: crate::Attiny,
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peripheral: crate::pac::ADC,
156+
settings: AdcSettings,
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apply_settings: |peripheral, settings| {
158+
apply_clock(peripheral, settings);
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peripheral.amiscr.write(|w| match settings.ref_voltage {
160+
ReferenceVoltage::Aref => w.arefen().set_bit(),
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_ => w.arefen().clear_bit(),
162+
});
163+
peripheral.admux.write(|w| match settings.ref_voltage {
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ReferenceVoltage::Aref => w.refs().avcc(),
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ReferenceVoltage::AVcc => w.refs().avcc(),
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ReferenceVoltage::Internal1_1 => w.refs().internal_11(),
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ReferenceVoltage::Internal2_56 => w.refs().internal_256(),
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});
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},
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channel_id: crate::pac::adc::admux::MUX_A,
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set_channel: |peripheral, id| {
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peripheral.admux.modify(|_, w| w.mux().variant(id));
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},
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pins: {
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port::PA0: (crate::pac::adc::admux::MUX_A::ADC0, didr0::adc0d),
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port::PA1: (crate::pac::adc::admux::MUX_A::ADC1, didr0::adc1d),
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port::PA2: (crate::pac::adc::admux::MUX_A::ADC2, didr0::adc2d),
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port::PA3: (crate::pac::adc::admux::MUX_A::ADC3, didr0::adc3d),
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port::PA4: (crate::pac::adc::admux::MUX_A::ADC4, didr0::adc4d),
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port::PA5: (crate::pac::adc::admux::MUX_A::ADC5, didr0::adc5d),
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port::PA6: (crate::pac::adc::admux::MUX_A::ADC6, didr0::adc6d),
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port::PA7: (crate::pac::adc::admux::MUX_A::ADC7, didr0::adc7d),
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port::PB5: (crate::pac::adc::admux::MUX_A::ADC8, didr1::adc8d),
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port::PB6: (crate::pac::adc::admux::MUX_A::ADC9, didr1::adc9d),
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port::PB7: (crate::pac::adc::admux::MUX_A::ADC10, didr1::adc10d),
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},
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channels: {
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channel::AVcc_4: crate::pac::adc::admux::MUX_A::ADC_AVCC_4,
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channel::Vbg: crate::pac::adc::admux::MUX_A::ADC_VBG,
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channel::Gnd: crate::pac::adc::admux::MUX_A::ADC_GND,
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channel::Temperature: crate::pac::adc::admux::MUX_A::TEMPSENS,
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},
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}

‎mcu/attiny-hal/src/lib.rs

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//! **Note**: This version of the documentation was built for
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#![cfg_attr(feature = "attiny85", doc = "**ATtiny85**.")]
99
#![cfg_attr(feature = "attiny88", doc = "**ATtiny88**.")]
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#![cfg_attr(feature = "attiny167", doc = "**ATtiny167**.")]
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//! This means that only items which are available for this MCU are visible. If you are using
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//! a different chip, try building the documentation locally with:
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//!
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* attiny85
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* attiny88
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* attiny167
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"
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);
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@@ -39,6 +41,10 @@ pub use avr_device::attiny85 as pac;
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#[cfg(feature = "attiny88")]
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pub use avr_device::attiny88 as pac;
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/// Reexport of `attiny167` from `avr-device`
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#[cfg(feature = "attiny167")]
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pub use avr_device::attiny167 as pac;
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/// See [`avr_device::entry`](https://docs.rs/avr-device/latest/avr_device/attr.entry.html).
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#[cfg(feature = "rt")]
4450
pub use avr_device::entry;
@@ -49,6 +55,11 @@ pub use pac::Peripherals;
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pub use avr_hal_generic::clock;
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pub use avr_hal_generic::delay;
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58+
#[cfg(feature = "device-selected")]
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pub mod adc;
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#[cfg(feature = "device-selected")]
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pub use adc::Adc;
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5263
#[cfg(feature = "device-selected")]
5364
pub mod port;
5465
#[cfg(feature = "device-selected")]
@@ -80,3 +91,10 @@ macro_rules! pins {
8091
$crate::Pins::new($p.PORTA, $p.PORTB, $p.PORTC, $p.PORTD)
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};
8293
}
94+
#[cfg(feature = "attiny167")]
95+
#[macro_export]
96+
macro_rules! pins {
97+
($p:expr) => {
98+
$crate::Pins::new($p.PORTA, $p.PORTB)
99+
};
100+
}

‎mcu/attiny-hal/src/port.rs

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#[cfg(feature = "attiny167")]
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avr_hal_generic::impl_port_traditional! {
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enum Ports {
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PORTA: (crate::pac::PORTA, porta, pina, ddra),
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PORTB: (crate::pac::PORTB, portb, pinb, ddrb),
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}
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pub struct Pins {
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pa0: PA0 = (crate::pac::PORTA, PORTA, 0, porta, pina, ddra),
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pa1: PA1 = (crate::pac::PORTA, PORTA, 1, porta, pina, ddra),
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pa2: PA2 = (crate::pac::PORTA, PORTA, 2, porta, pina, ddra),
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pa3: PA3 = (crate::pac::PORTA, PORTA, 3, porta, pina, ddra),
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pa4: PA4 = (crate::pac::PORTA, PORTA, 4, porta, pina, ddra),
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pa5: PA5 = (crate::pac::PORTA, PORTA, 5, porta, pina, ddra),
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pa6: PA6 = (crate::pac::PORTA, PORTA, 6, porta, pina, ddra),
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pa7: PA7 = (crate::pac::PORTA, PORTA, 7, porta, pina, ddra),
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pb0: PB0 = (crate::pac::PORTB, PORTB, 0, portb, pinb, ddrb),
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pb1: PB1 = (crate::pac::PORTB, PORTB, 1, portb, pinb, ddrb),
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pb2: PB2 = (crate::pac::PORTB, PORTB, 2, portb, pinb, ddrb),
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pb3: PB3 = (crate::pac::PORTB, PORTB, 3, portb, pinb, ddrb),
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pb4: PB4 = (crate::pac::PORTB, PORTB, 4, portb, pinb, ddrb),
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pb5: PB5 = (crate::pac::PORTB, PORTB, 5, portb, pinb, ddrb),
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pb6: PB6 = (crate::pac::PORTB, PORTB, 6, portb, pinb, ddrb),
24+
pb7: PB7 = (crate::pac::PORTB, PORTB, 7, portb, pinb, ddrb),
25+
}
26+
}
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#[cfg(feature = "attiny84")]
229
avr_hal_generic::impl_port_traditional! {
330
enum Ports {

‎mcu/attiny-hal/src/spi.rs

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@@ -20,3 +20,22 @@ avr_hal_generic::impl_spi! {
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miso: port::PB4,
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cs: port::PB2,
2222
}
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24+
#[cfg(feature = "attiny167")]
25+
pub type Spi = avr_hal_generic::spi::Spi<
26+
crate::Atmega,
27+
crate::pac::SPI,
28+
port::PA5,
29+
port::PA4,
30+
port::PA2,
31+
port::PA6,
32+
>;
33+
#[cfg(feature = "attiny167")]
34+
avr_hal_generic::impl_spi! {
35+
hal: crate::Atmega,
36+
peripheral: crate::pac::SPI,
37+
sclk: port::PA5,
38+
mosi: port::PA4,
39+
miso: port::PA2,
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cs: port::PA6,
41+
}

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