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bsp: k230: support canmv board
Some changes to support canmv board, such as: - Address constant, some may need be set as configuration later. - link script - build script Signed-off-by: Wang Chen <unicorn_wang@outlook.com>
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5 files changed

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-12
lines changed

5 files changed

+188
-12
lines changed

‎bsp/k230/board/board.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -24,14 +24,14 @@
2424
#include "page.h"
2525

2626
/* respect to boot loader, must be 0xFFFFFFC000200000 */
27-
RT_STATIC_ASSERT(kmem_region, KERNEL_VADDR_START == 0xFFFFFFC000220000);
27+
RT_STATIC_ASSERT(kmem_region, KERNEL_VADDR_START == 0xffffffc000020000);
2828

2929
rt_region_t init_page_region = {(rt_size_t)RT_HW_PAGE_START, (rt_size_t)RT_HW_PAGE_END};
3030

3131
extern size_t MMUTable[];
3232

3333
struct mem_desc platform_mem_desc[] = {
34-
{KERNEL_VADDR_START, (rt_size_t)RT_HW_PAGE_END - 1, (rt_size_t)ARCH_MAP_FAILED, NORMAL_MEM},
34+
{KERNEL_VADDR_START, (rt_size_t)0xFFFFFFC020000000 - 1, (rt_size_t)ARCH_MAP_FAILED, NORMAL_MEM},
3535
};
3636

3737
#define NUM_MEM_DESC (sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]))

‎bsp/k230/board/board.h

Lines changed: 172 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,18 +16,188 @@
1616
extern unsigned int __sram_size;
1717
extern unsigned int __sram_base;
1818
extern unsigned int __sram_end;
19-
#define RAM_END (rt_size_t)((void *)&__sram_end)
19+
#define RAM_END (rt_size_t)((void *)&__sram_end)
2020

2121
extern unsigned int __bss_start;
2222
extern unsigned int __bss_end;
2323

2424
#define RT_HW_HEAP_BEGIN ((void *)&__bss_end)
25-
#define RT_HW_HEAP_END ((void *)(((rt_size_t)RT_HW_HEAP_BEGIN) + 8 * 1024 * 1024))
25+
#define RT_HW_HEAP_END ((void *)(((rt_size_t)RT_HW_HEAP_BEGIN) + 0x2000000 ))
2626

2727
#define RT_HW_PAGE_START ((void *)((rt_size_t)RT_HW_HEAP_END + sizeof(rt_size_t)))
2828
#define RT_HW_PAGE_END ((void *)(RAM_END))
2929

3030
void rt_hw_board_init(void);
3131
void rt_init_user_mem(struct rt_thread *thread, const char *name, unsigned long *entry);
3232

33+
#define TIMER_CLK_FREQ (27000000)
34+
35+
/* From K230 Technical Reference Manual, chapter 1.5 Address Space mapping */
36+
#define SRAM_BASE_ADDR (0x80200000UL)
37+
#define SRAM_IO_SIZE (0x00200000UL)
38+
39+
#define KPU_BASE_ADDR (0x80400000UL)
40+
#define KPU_IO_SIZE (0x00000800UL)
41+
42+
#define FFT_BASE_ADDR (0x80400800UL)
43+
#define FFT_IO_SIZE (0x00000400UL)
44+
45+
#define AI2D_BASE_ADDR (0x80400C00UL)
46+
#define AI2D_IO_SIZE (0x00000400UL)
47+
48+
#define GSDMA_BASE_ADDR (0x80800000UL)
49+
#define GSDMA_IO_SIZE (0x00004000UL)
50+
51+
#define DMA_BASE_ADDR (0x80804000UL)
52+
#define DMA_IO_SIZE (0x00004000UL)
53+
54+
#define DECOMP_BASE_ADDR (0x80808000UL)
55+
#define DECOMP_IO_SIZE (0x00004000UL)
56+
57+
#define NON_AI2D_BASE_ADDR (0x8080C000UL)
58+
#define NON_AI2D_IO_SIZE (0x00004000UL)
59+
60+
#define ISP_BASE_ADDR (0x90000000UL)
61+
#define ISP_IO_SIZE (0x00008000UL)
62+
63+
#define DEWARP_BASE_ADDR (0x90008000UL)
64+
#define DEWARP_IO_SIZE (0x00001000UL)
65+
66+
#define CSI_BASE_ADDR (0x90009000UL)
67+
#define CSI_IO_SIZE (0x00002000UL)
68+
69+
#define VPU_BASE_ADDR (0x90400000UL)
70+
#define VPU_IO_SIZE (0x00010000UL)
71+
72+
/*2.5D*/
73+
#define TAAH_GPU_BASE_ADDR (0x90800000UL)
74+
#define TAAH_GPU_IO_SIZE (0x00040000UL)
75+
76+
#define VO_BASE_ADDR (0x90840000UL)
77+
#define VO_IO_SIZE (0x00010000UL)
78+
79+
#define DSI_BASE_ADDR (0x90850000UL)
80+
#define DSI_IO_SIZE (0x00001000UL)
81+
82+
#define GPU_ENGINE_BASE_ADDR (0x90A00000UL)
83+
#define GPU_ENGINE_IO_SIZE (0x00000800UL)
84+
85+
#define PMU_BASE_ADDR (0x91000000UL)
86+
#define PMU_IO_SIZE (0x00000C00UL)
87+
88+
#define RTC_BASE_ADDR (0x91000C00UL)
89+
#define RTC_IO_SIZE (0x00000400UL)
90+
91+
#define CMU_BASE_ADDR (0x91100000UL)
92+
#define CMU_IO_SIZE (0x00001000UL)
93+
94+
#define RMU_BASE_ADDR (0x91101000UL)
95+
#define RMU_IO_SIZE (0x00001000UL)
96+
97+
#define BOOT_BASE_ADDR (0x91102000UL)
98+
#define BOOT_IO_SIZE (0x00001000UL)
99+
100+
#define PWR_BASE_ADDR (0x91103000UL)
101+
#define PWR_IO_SIZE (0x00001000UL)
102+
103+
#define MAILBOX_BASE_ADDR (0x91104000UL)
104+
#define MAILBOX_IO_SIZE (0x00001000UL)
105+
106+
#define IOMUX_BASE_ADDR (0x91105000UL)
107+
#define IOMUX_IO_SIZE (0x00000800UL)
108+
109+
#define HW_TIMER_BASE_ADDR (0x91105800UL)
110+
#define HW_TIMER_IO_SIZE (0x00000800UL)
111+
112+
#define WDT0_BASE_ADDR (0x91106000UL)
113+
#define WDT0_IO_SIZE (0x00000800UL)
114+
115+
#define WDT1_BASE_ADDR (0x91106800UL)
116+
#define WDT1_IO_SIZE (0x00000800UL)
117+
118+
#define TS_BASE_ADDR (0x91107000UL)
119+
#define TS_IO_SIZE (0x00000800UL)
120+
121+
#define HDI_BASE_ADDR (0x91107800UL)
122+
#define HDI_IO_SIZE (0x00000800UL)
123+
124+
#define STC_BASE_ADDR (0x91108000UL)
125+
#define STC_IO_SIZE (0x00001000UL)
126+
127+
#define BOOTROM_BASE_ADDR (0x91200000UL)
128+
#define BOOTROM_IO_SIZE (0x00010000UL)
129+
130+
#define SECURITY_BASE_ADDR (0x91210000UL)
131+
#define SECURITY_IO_SIZE (0x00008000UL)
132+
133+
#define UART0_BASE_ADDR (0x91400000UL)
134+
#define UART0_IO_SIZE (0x00001000UL)
135+
136+
#define UART1_BASE_ADDR (0x91401000UL)
137+
#define UART1_IO_SIZE (0x00001000UL)
138+
139+
#define UART2_BASE_ADDR (0x91402000UL)
140+
#define UART2_IO_SIZE (0x00001000UL)
141+
142+
#define UART3_BASE_ADDR (0x91403000UL)
143+
#define UART3_IO_SIZE (0x00001000UL)
144+
145+
#define UART4_BASE_ADDR (0x91404000UL)
146+
#define UART4_IO_SIZE (0x00001000UL)
147+
148+
#define I2C0_BASE_ADDR (0x91405000UL)
149+
#define I2C0_IO_SIZE (0x00001000UL)
150+
151+
#define I2C1_BASE_ADDR (0x91406000UL)
152+
#define I2C1_IO_SIZE (0x00001000UL)
153+
154+
#define I2C2_BASE_ADDR (0x91407000UL)
155+
#define I2C2_IO_SIZE (0x00001000UL)
156+
157+
#define I2C3_BASE_ADDR (0x91408000UL)
158+
#define I2C3_IO_SIZE (0x00001000UL)
159+
160+
#define I2C4_BASE_ADDR (0x91409000UL)
161+
#define I2C4_IO_SIZE (0x00001000UL)
162+
163+
#define PWM_BASE_ADDR (0x9140A000UL)
164+
#define PWM_IO_SIZE (0x00001000UL)
165+
166+
#define GPIO0_BASE_ADDR (0x9140B000UL)
167+
#define GPIO0_IO_SIZE (0x00001000UL)
168+
169+
#define GPIO1_BASE_ADDR (0x9140C000UL)
170+
#define GPIO1_IO_SIZE (0x00001000UL)
171+
172+
#define ADC_BASE_ADDR (0x9140D000UL)
173+
#define ADC_IO_SIZE (0x00001000UL)
174+
175+
#define CODEC_BASE_ADDR (0x9140E000UL)
176+
#define CODEC_IO_SIZE (0x00001000UL)
177+
178+
#define AUDIO_BASE_ADDR (0x9140F000UL)
179+
#define AUDIO_IO_SIZE (0x00001000UL)
180+
181+
#define USB2_BASE_ADDR (0x91500000UL)
182+
#define USB2_IO_SIZE (0x00080000UL)
183+
184+
#define SD_HC_BASE_ADDR (0x91580000UL)
185+
#define SD_HC_IO_SIZE (0x00002000UL)
186+
187+
#define SPI_QOPI_BASE_ADDR (0x91582000UL)
188+
#define SPI_QOPI_IO_SIZE (0x00002000UL)
189+
190+
#define SPI_OPI_BASE_ADDR (0x91584000UL)
191+
#define SPI_OPI_IO_SIZE (0x00001000UL)
192+
193+
#define HI_SYS_CONFIG_BASE_ADDR (0x91585000UL)
194+
#define HI_SYS_CONFIG_IO_SIZE (0x00000400UL)
195+
196+
#define DDRC_CONF_BASE_ADDR (0x98000000UL)
197+
#define DDRC_CONF_IO_SIZE (0x02000000UL)
198+
199+
#define SPI_XIP_FLASH_BASE_ADDR (0xC0000000UL)
200+
#define SPI_XIP_FLASH_IO_SIZE (0x08000000UL)
201+
202+
#define IO_SPACE_BASE_ADDR (KPU_BASE_ADDR)
33203
#endif

‎bsp/k230/link.lds

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ OUTPUT_ARCH( "riscv" )
2222

2323
MEMORY
2424
{
25-
SRAM(wx) : ORIGIN = 0xFFFFFFC000220000, LENGTH = 64M - 128K
25+
SRAM : ORIGIN = 0xffffffc000020000, LENGTH = 262012K
2626
}
2727

2828
ENTRY(_start)

‎bsp/k230/link_stacksize.lds

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
__STACKSIZE__ = 8192;
1+
__STACKSIZE__ = 65536;

‎bsp/k230/rtconfig.py

Lines changed: 12 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
import os
2+
import re
23

34
# toolchains options
45
ARCH ='risc-v'
@@ -13,14 +14,18 @@
1314

1415
if CROSS_TOOL == 'gcc':
1516
PLATFORM = 'gcc'
16-
EXEC_PATH = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin'
17+
EXEC_PATH = r'/opt/toolchain/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_rtt/bin'
1718
else:
1819
print('Please make sure your toolchains is GNU GCC!')
1920
exit(0)
2021

21-
EXEC_PATH = os.getenv('RTT_EXEC_PATH', EXEC_PATH)
22+
if os.getenv('RTT_EXEC_PATH'):
23+
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
2224

23-
BUILD = 'debug'
25+
if re.match("-DDBGLV=0", os.getenv('KCFLAGS', '-DDBGLV=0')):
26+
BUILD = 'release'
27+
else:
28+
BUILD = 'debug'
2429

2530
if PLATFORM == 'gcc':
2631
# toolchains
@@ -36,18 +41,19 @@
3641
OBJDUMP = PREFIX + 'objdump'
3742
OBJCPY = PREFIX + 'objcopy'
3843

39-
DEVICE = ' -mcmodel=medany -march=rv64imafdc -mabi=lp64'
44+
DEVICE = ' -mcmodel=medany -march=rv64imafdcv -mabi=lp64d'
4045
CFLAGS = DEVICE + ' -Wno-cpp -fvar-tracking -ffreestanding -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -D_POSIX_SOURCE '
4146
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__'
4247
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds' + ' -lsupc++ -lgcc -static'
4348
CPATH = ''
4449
LPATH = ''
4550

4651
if BUILD == 'debug':
47-
CFLAGS += ' -O2 -g -gdwarf-2'
48-
AFLAGS += ' -g -gdwarf-2'
52+
CFLAGS += ' -O0 -gdwarf-2'
53+
AFLAGS += ' -gdwarf-2'
4954
else:
5055
CFLAGS += ' -O2 -g -gdwarf-2'
56+
CFLAGS += ' ' + os.getenv('KCFLAGS', '-DDBGLV=0')
5157

5258
CXXFLAGS = CFLAGS
5359

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