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[Hexagon] Use MCRegister. NFC
1 parent 01b7e65 commit d150101

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2 files changed

+10
-10
lines changed

2 files changed

+10
-10
lines changed

llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -460,8 +460,8 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
460460
TmpInst.setOpcode(Hexagon::A2_combinew);
461461
TmpInst.addOperand(MappedInst.getOperand(0));
462462
MCOperand &MO1 = MappedInst.getOperand(1);
463-
unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi);
464-
unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo);
463+
MCRegister High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi);
464+
MCRegister Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo);
465465
// Add a new operand for the second register in the pair.
466466
TmpInst.addOperand(MCOperand::createReg(High));
467467
TmpInst.addOperand(MCOperand::createReg(Low));
@@ -537,8 +537,8 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
537537
// Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
538538
case Hexagon::A2_tfrp: {
539539
MCOperand &MO = MappedInst.getOperand(1);
540-
unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
541-
unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
540+
MCRegister High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
541+
MCRegister Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
542542
MO.setReg(High);
543543
// Add a new operand for the second register in the pair.
544544
MappedInst.addOperand(MCOperand::createReg(Low));
@@ -549,8 +549,8 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
549549
case Hexagon::A2_tfrpt:
550550
case Hexagon::A2_tfrpf: {
551551
MCOperand &MO = MappedInst.getOperand(2);
552-
unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
553-
unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
552+
MCRegister High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
553+
MCRegister Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
554554
MO.setReg(High);
555555
// Add a new operand for the second register in the pair.
556556
MappedInst.addOperand(MCOperand::createReg(Low));
@@ -563,8 +563,8 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
563563
case Hexagon::A2_tfrptnew:
564564
case Hexagon::A2_tfrpfnew: {
565565
MCOperand &MO = MappedInst.getOperand(2);
566-
unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
567-
unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
566+
MCRegister High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
567+
MCRegister Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
568568
MO.setReg(High);
569569
// Add a new operand for the second register in the pair.
570570
MappedInst.addOperand(MCOperand::createReg(Low));

llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -593,8 +593,8 @@ void HexagonCopyToCombine::combine(MachineInstr &I1, MachineInstr &I2,
593593
llvm_unreachable("Unexpected register class");
594594

595595
// Get the double word register.
596-
unsigned DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC);
597-
assert(DoubleRegDest != 0 && "Expect a valid register");
596+
MCRegister DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC);
597+
assert(DoubleRegDest.isValid() && "Expect a valid register");
598598

599599
// Setup source operands.
600600
MachineOperand &LoOperand = IsI1Loreg ? I1.getOperand(1) : I2.getOperand(1);

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