Skip to content

Commit c268a3f

Browse files
committed
DAG: Fix extract of load combine with mismatched vector element type
Fix the case where the vector element type of the loaded extractelement input does not match the result type of the extract. This fixes a regression reported after c55a765
1 parent f7b3559 commit c268a3f

File tree

2 files changed

+21
-1
lines changed

2 files changed

+21
-1
lines changed

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23188,7 +23188,7 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
2318823188
auto *VecLoad = dyn_cast<LoadSDNode>(VecOp);
2318923189
if (VecLoad && VecLoad->isSimple()) {
2319023190
if (SDValue Scalarized = TLI.scalarizeExtractedVectorLoad(
23191-
ExtVT, SDLoc(N), VecVT, Index, VecLoad, DAG)) {
23191+
ScalarVT, SDLoc(N), VecVT, Index, VecLoad, DAG)) {
2319223192
++OpsNarrowed;
2319323193
return Scalarized;
2319423194
}
Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,20 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc -mtriple=armv7-unknown-linux-gnueabihf < %s | FileCheck %s
3+
4+
; Check for assertion when extractelement of load optimization
5+
; involves a result element type different from the input vector
6+
; element type.
7+
8+
define i8 @baz(ptr %ptr, i32 %arg) {
9+
; CHECK-LABEL: baz:
10+
; CHECK: @ %bb.0: @ %bb
11+
; CHECK-NEXT: add r1, r1, r1
12+
; CHECK-NEXT: and r1, r1, #3
13+
; CHECK-NEXT: ldr r0, [r0, r1, lsl #2]
14+
; CHECK-NEXT: bx lr
15+
bb:
16+
%load = load <2 x i64>, ptr %ptr, align 8
17+
%extractelement = extractelement <2 x i64> %load, i32 %arg
18+
%trunc = trunc i64 %extractelement to i8
19+
ret i8 %trunc
20+
}

0 commit comments

Comments
 (0)