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[PowerPC] Add load/store support for v2048i1 and DMF cryptography instructions (llvm#136145)
This commit adds support for loading and storing v2048i1 DMR pairs and introduces Dense Math Facility cryptography instructions: DMSHA2HASH, DMSHA3HASH, and DMXXSHAPAD, along with their corresponding intrinsics and tests.
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9 files changed

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-30
lines changed

9 files changed

+570
-30
lines changed

‎llvm/include/llvm/IR/Intrinsics.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -544,6 +544,7 @@ def llvm_v128i1_ty : LLVMType<v128i1>; // 128 x i1
544544
def llvm_v256i1_ty : LLVMType<v256i1>; // 256 x i1
545545
def llvm_v512i1_ty : LLVMType<v512i1>; // 512 x i1
546546
def llvm_v1024i1_ty : LLVMType<v1024i1>; //1024 x i1
547+
def llvm_v2048i1_ty : LLVMType<v2048i1>; //2048 x i1
547548
def llvm_v4096i1_ty : LLVMType<v4096i1>; //4096 x i1
548549

549550
def llvm_v1i8_ty : LLVMType<v1i8>; // 1 x i8

‎llvm/include/llvm/IR/IntrinsicsPowerPC.td

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1778,6 +1778,20 @@ let TargetPrefix = "ppc" in {
17781778
defm int_ppc_mma_pmdmxvf16gerx2 :
17791779
PowerPC_MMA_DMR_Intrinsic<[llvm_v256i1_ty, llvm_v16i8_ty, llvm_i32_ty,
17801780
llvm_i32_ty, llvm_i32_ty]>;
1781+
def int_ppc_mma_dmsha2hash :
1782+
DefaultAttrsIntrinsic<[llvm_v1024i1_ty], [llvm_v1024i1_ty,
1783+
llvm_v1024i1_ty, llvm_i32_ty],
1784+
[IntrNoMem, ImmArg<ArgIndex<2>>]>;
1785+
1786+
def int_ppc_mma_dmsha3hash :
1787+
DefaultAttrsIntrinsic<[llvm_v2048i1_ty], [llvm_v2048i1_ty,
1788+
llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1789+
1790+
def int_ppc_mma_dmxxshapad :
1791+
DefaultAttrsIntrinsic<[llvm_v1024i1_ty], [llvm_v1024i1_ty,
1792+
llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty,
1793+
llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<2>>,
1794+
ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>]>;
17811795
}
17821796

17831797
// XL Compat intrinsics.

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 115 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -1361,8 +1361,11 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
13611361
if (Subtarget.isISAFuture()) {
13621362
addRegisterClass(MVT::v512i1, &PPC::WACCRCRegClass);
13631363
addRegisterClass(MVT::v1024i1, &PPC::DMRRCRegClass);
1364+
addRegisterClass(MVT::v2048i1, &PPC::DMRpRCRegClass);
13641365
setOperationAction(ISD::LOAD, MVT::v1024i1, Custom);
13651366
setOperationAction(ISD::STORE, MVT::v1024i1, Custom);
1367+
setOperationAction(ISD::LOAD, MVT::v2048i1, Custom);
1368+
setOperationAction(ISD::STORE, MVT::v2048i1, Custom);
13661369
} else {
13671370
addRegisterClass(MVT::v512i1, &PPC::UACCRCRegClass);
13681371
}
@@ -11890,15 +11893,19 @@ SDValue PPCTargetLowering::LowerDMFVectorLoad(SDValue Op,
1189011893
SDValue LoadChain = LN->getChain();
1189111894
SDValue BasePtr = LN->getBasePtr();
1189211895
EVT VT = Op.getValueType();
11896+
bool IsV1024i1 = VT == MVT::v1024i1;
11897+
bool IsV2048i1 = VT == MVT::v2048i1;
1189311898

11894-
// Type v1024i1 is used for Dense Math dmr registers.
11895-
assert(VT == MVT::v1024i1 && "Unsupported type.");
11899+
// The types v1024i1 and v2048i1 are used for Dense Math dmr registers and
11900+
// Dense Math dmr pair registers, respectively.
11901+
assert((IsV1024i1 || IsV2048i1) && "Unsupported type.");
1189611902
assert((Subtarget.hasMMA() && Subtarget.isISAFuture()) &&
1189711903
"Dense Math support required.");
1189811904
assert(Subtarget.pairedVectorMemops() && "Vector pair support required.");
1189911905

11900-
SmallVector<SDValue, 4> Loads;
11901-
SmallVector<SDValue, 4> LoadChains;
11906+
SmallVector<SDValue, 8> Loads;
11907+
SmallVector<SDValue, 8> LoadChains;
11908+
1190211909
SDValue IntrinID = DAG.getConstant(Intrinsic::ppc_vsx_lxvp, dl, MVT::i32);
1190311910
SDValue LoadOps[] = {LoadChain, IntrinID, BasePtr};
1190411911
MachineMemOperand *MMO = LN->getMemOperand();
@@ -11934,11 +11941,36 @@ SDValue PPCTargetLowering::LowerDMFVectorLoad(SDValue Op,
1193411941
SDValue HiSub = DAG.getTargetConstant(PPC::sub_wacc_hi, dl, MVT::i32);
1193511942
SDValue RC = DAG.getTargetConstant(PPC::DMRRCRegClassID, dl, MVT::i32);
1193611943
const SDValue Ops[] = {RC, Lo, LoSub, Hi, HiSub};
11944+
1193711945
SDValue Value =
1193811946
SDValue(DAG.getMachineNode(PPC::REG_SEQUENCE, dl, MVT::v1024i1, Ops), 0);
1193911947

11940-
SDValue RetOps[] = {Value, TF};
11941-
return DAG.getMergeValues(RetOps, dl);
11948+
if (IsV1024i1) {
11949+
return DAG.getMergeValues({Value, TF}, dl);
11950+
}
11951+
11952+
// Handle Loads for V2048i1 which represents a dmr pair.
11953+
SDValue DmrPValue;
11954+
SDValue Dmr1Lo(DAG.getMachineNode(PPC::DMXXINSTDMR512, dl, MVT::v512i1,
11955+
Loads[4], Loads[5]),
11956+
0);
11957+
SDValue Dmr1Hi(DAG.getMachineNode(PPC::DMXXINSTDMR512_HI, dl, MVT::v512i1,
11958+
Loads[6], Loads[7]),
11959+
0);
11960+
const SDValue Dmr1Ops[] = {RC, Dmr1Lo, LoSub, Dmr1Hi, HiSub};
11961+
SDValue Dmr1Value = SDValue(
11962+
DAG.getMachineNode(PPC::REG_SEQUENCE, dl, MVT::v1024i1, Dmr1Ops), 0);
11963+
11964+
SDValue Dmr0Sub = DAG.getTargetConstant(PPC::sub_dmr0, dl, MVT::i32);
11965+
SDValue Dmr1Sub = DAG.getTargetConstant(PPC::sub_dmr1, dl, MVT::i32);
11966+
11967+
SDValue DmrPRC = DAG.getTargetConstant(PPC::DMRpRCRegClassID, dl, MVT::i32);
11968+
const SDValue DmrPOps[] = {DmrPRC, Value, Dmr0Sub, Dmr1Value, Dmr1Sub};
11969+
11970+
DmrPValue = SDValue(
11971+
DAG.getMachineNode(PPC::REG_SEQUENCE, dl, MVT::v2048i1, DmrPOps), 0);
11972+
11973+
return DAG.getMergeValues({DmrPValue, TF}, dl);
1194211974
}
1194311975

1194411976
SDValue PPCTargetLowering::LowerVectorLoad(SDValue Op,
@@ -11949,7 +11981,7 @@ SDValue PPCTargetLowering::LowerVectorLoad(SDValue Op,
1194911981
SDValue BasePtr = LN->getBasePtr();
1195011982
EVT VT = Op.getValueType();
1195111983

11952-
if (VT == MVT::v1024i1)
11984+
if (VT == MVT::v1024i1 || VT == MVT::v2048i1)
1195311985
return LowerDMFVectorLoad(Op, DAG);
1195411986

1195511987
if (VT != MVT::v256i1 && VT != MVT::v512i1)
@@ -11996,34 +12028,88 @@ SDValue PPCTargetLowering::LowerDMFVectorStore(SDValue Op,
1199612028
StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
1199712029
SDValue StoreChain = SN->getChain();
1199812030
SDValue BasePtr = SN->getBasePtr();
11999-
SmallVector<SDValue, 4> Values;
12000-
SmallVector<SDValue, 4> Stores;
12031+
SmallVector<SDValue, 8> Values;
12032+
SmallVector<SDValue, 8> Stores;
1200112033
EVT VT = SN->getValue().getValueType();
12034+
bool IsV1024i1 = VT == MVT::v1024i1;
12035+
bool IsV2048i1 = VT == MVT::v2048i1;
1200212036

12003-
// Type v1024i1 is used for Dense Math dmr registers.
12004-
assert(VT == MVT::v1024i1 && "Unsupported type.");
12037+
// The types v1024i1 and v2048i1 are used for Dense Math dmr registers and
12038+
// Dense Math dmr pair registers, respectively.
12039+
assert((IsV1024i1 || IsV2048i1) && "Unsupported type.");
1200512040
assert((Subtarget.hasMMA() && Subtarget.isISAFuture()) &&
1200612041
"Dense Math support required.");
1200712042
assert(Subtarget.pairedVectorMemops() && "Vector pair support required.");
1200812043

12009-
SDValue Lo(
12010-
DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, MVT::v512i1,
12011-
Op.getOperand(1),
12012-
DAG.getTargetConstant(PPC::sub_wacc_lo, dl, MVT::i32)),
12013-
0);
12014-
SDValue Hi(
12015-
DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, MVT::v512i1,
12016-
Op.getOperand(1),
12017-
DAG.getTargetConstant(PPC::sub_wacc_hi, dl, MVT::i32)),
12018-
0);
1201912044
EVT ReturnTypes[] = {MVT::v256i1, MVT::v256i1};
12020-
MachineSDNode *ExtNode =
12021-
DAG.getMachineNode(PPC::DMXXEXTFDMR512, dl, ReturnTypes, Lo);
12022-
Values.push_back(SDValue(ExtNode, 0));
12023-
Values.push_back(SDValue(ExtNode, 1));
12024-
ExtNode = DAG.getMachineNode(PPC::DMXXEXTFDMR512_HI, dl, ReturnTypes, Hi);
12025-
Values.push_back(SDValue(ExtNode, 0));
12026-
Values.push_back(SDValue(ExtNode, 1));
12045+
if (IsV1024i1) {
12046+
SDValue Lo(DAG.getMachineNode(
12047+
TargetOpcode::EXTRACT_SUBREG, dl, MVT::v512i1,
12048+
Op.getOperand(1),
12049+
DAG.getTargetConstant(PPC::sub_wacc_lo, dl, MVT::i32)),
12050+
0);
12051+
SDValue Hi(DAG.getMachineNode(
12052+
TargetOpcode::EXTRACT_SUBREG, dl, MVT::v512i1,
12053+
Op.getOperand(1),
12054+
DAG.getTargetConstant(PPC::sub_wacc_hi, dl, MVT::i32)),
12055+
0);
12056+
MachineSDNode *ExtNode =
12057+
DAG.getMachineNode(PPC::DMXXEXTFDMR512, dl, ReturnTypes, Lo);
12058+
Values.push_back(SDValue(ExtNode, 0));
12059+
Values.push_back(SDValue(ExtNode, 1));
12060+
ExtNode = DAG.getMachineNode(PPC::DMXXEXTFDMR512_HI, dl, ReturnTypes, Hi);
12061+
Values.push_back(SDValue(ExtNode, 0));
12062+
Values.push_back(SDValue(ExtNode, 1));
12063+
} else {
12064+
// This corresponds to v2048i1 which represents a dmr pair.
12065+
SDValue Dmr0(
12066+
DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, MVT::v1024i1,
12067+
Op.getOperand(1),
12068+
DAG.getTargetConstant(PPC::sub_dmr0, dl, MVT::i32)),
12069+
0);
12070+
12071+
SDValue Dmr1(
12072+
DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, MVT::v1024i1,
12073+
Op.getOperand(1),
12074+
DAG.getTargetConstant(PPC::sub_dmr1, dl, MVT::i32)),
12075+
0);
12076+
12077+
SDValue Dmr0Lo(DAG.getMachineNode(
12078+
TargetOpcode::EXTRACT_SUBREG, dl, MVT::v512i1, Dmr0,
12079+
DAG.getTargetConstant(PPC::sub_wacc_lo, dl, MVT::i32)),
12080+
0);
12081+
12082+
SDValue Dmr0Hi(DAG.getMachineNode(
12083+
TargetOpcode::EXTRACT_SUBREG, dl, MVT::v512i1, Dmr0,
12084+
DAG.getTargetConstant(PPC::sub_wacc_hi, dl, MVT::i32)),
12085+
0);
12086+
12087+
SDValue Dmr1Lo(DAG.getMachineNode(
12088+
TargetOpcode::EXTRACT_SUBREG, dl, MVT::v512i1, Dmr1,
12089+
DAG.getTargetConstant(PPC::sub_wacc_lo, dl, MVT::i32)),
12090+
0);
12091+
12092+
SDValue Dmr1Hi(DAG.getMachineNode(
12093+
TargetOpcode::EXTRACT_SUBREG, dl, MVT::v512i1, Dmr1,
12094+
DAG.getTargetConstant(PPC::sub_wacc_hi, dl, MVT::i32)),
12095+
0);
12096+
12097+
MachineSDNode *ExtNode =
12098+
DAG.getMachineNode(PPC::DMXXEXTFDMR512, dl, ReturnTypes, Dmr0Lo);
12099+
Values.push_back(SDValue(ExtNode, 0));
12100+
Values.push_back(SDValue(ExtNode, 1));
12101+
ExtNode =
12102+
DAG.getMachineNode(PPC::DMXXEXTFDMR512_HI, dl, ReturnTypes, Dmr0Hi);
12103+
Values.push_back(SDValue(ExtNode, 0));
12104+
Values.push_back(SDValue(ExtNode, 1));
12105+
ExtNode = DAG.getMachineNode(PPC::DMXXEXTFDMR512, dl, ReturnTypes, Dmr1Lo);
12106+
Values.push_back(SDValue(ExtNode, 0));
12107+
Values.push_back(SDValue(ExtNode, 1));
12108+
ExtNode =
12109+
DAG.getMachineNode(PPC::DMXXEXTFDMR512_HI, dl, ReturnTypes, Dmr1Hi);
12110+
Values.push_back(SDValue(ExtNode, 0));
12111+
Values.push_back(SDValue(ExtNode, 1));
12112+
}
1202712113

1202812114
if (Subtarget.isLittleEndian())
1202912115
std::reverse(Values.begin(), Values.end());
@@ -12062,7 +12148,7 @@ SDValue PPCTargetLowering::LowerVectorStore(SDValue Op,
1206212148
SDValue Value2 = SN->getValue();
1206312149
EVT StoreVT = Value.getValueType();
1206412150

12065-
if (StoreVT == MVT::v1024i1)
12151+
if (StoreVT == MVT::v1024i1 || StoreVT == MVT::v2048i1)
1206612152
return LowerDMFVectorStore(Op, DAG);
1206712153

1206812154
if (StoreVT != MVT::v256i1 && StoreVT != MVT::v512i1)

‎llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td

Lines changed: 123 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -333,6 +333,63 @@ multiclass DMR_NEG_UM_M284_XOXORd11188<bits<6> opcode, bits<8> xo, dag IOL,
333333
}
334334
}
335335

336+
class XForm_AT3_T1_AB3<bits<6> opcode, bits<5> o, bits<10> xo, dag OOL, dag IOL,
337+
string asmstr, list<dag> pattern>
338+
: I <opcode, OOL, IOL, asmstr, NoItinerary> {
339+
bits<3> AT;
340+
bits<3> AB;
341+
bits<1> T;
342+
343+
let Pattern = pattern;
344+
345+
let Inst{6-8} = AT{2-0};
346+
let Inst{9} = 0;
347+
let Inst{10} = T;
348+
let Inst{11-15} = o;
349+
let Inst{16-18} = AB{2-0};
350+
let Inst{19-20} = 0;
351+
let Inst{21-30} = xo;
352+
let Inst{31} = 0;
353+
}
354+
355+
class XForm_ATp2_SR5<bits<6> opcode, bits<5> o, bits<10> xo, dag OOL, dag IOL,
356+
string asmstr, list<dag> pattern>
357+
: I <opcode, OOL, IOL, asmstr, NoItinerary> {
358+
bits<2> ATp;
359+
bits<5> SR;
360+
361+
let Pattern = pattern;
362+
363+
let Inst{6-7} = ATp{1-0};
364+
let Inst{8-10} = 0;
365+
let Inst{11-15} = o;
366+
let Inst{16-20} = SR{4-0};
367+
let Inst{21-30} = xo;
368+
let Inst{31} = 0;
369+
}
370+
371+
class XX2Form_AT3_XB6_ID2_E1_BL2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
372+
string asmstr, list<dag> pattern>
373+
: I<opcode, OOL, IOL, asmstr, NoItinerary> {
374+
bits<3> AT;
375+
bits<6> XB;
376+
bits<2> ID;
377+
bits<1> E;
378+
bits<2> BL;
379+
380+
let Pattern = pattern;
381+
382+
let Inst{6-8} = AT{2-0};
383+
let Inst{9-10} = 0;
384+
let Inst{11-12} = ID{1-0};
385+
let Inst{13} = E;
386+
let Inst{14-15} = BL{1-0};
387+
let Inst{16-20} = XB{4-0};
388+
let Inst{21-29} = xo;
389+
let Inst{30} = XB{5};
390+
let Inst{31} = 0;
391+
}
392+
336393
let Predicates = [IsISAFuture] in {
337394
def DMXXEXTFDMR512 : XX3Form_AT3_XABp5_P1<60, 226,
338395
(outs vsrprc:$XAp, vsrprc:$XBp),
@@ -415,6 +472,27 @@ defm DMXVBF16GERX2 : DMR_NEG_UM_M284_XOXORf939a0<59, 74, (ins vsrprc:$XAp, vsrc:
415472
defm DMXVF16GERX2 : DMR_NEG_UM_M284_XOXORd11188<59, 66, (ins vsrprc:$XAp, vsrc:$XB),
416473
"dmxvf16gerx2", "$AT, $XAp, $XB">;
417474

475+
// DMF cryptography [support] Instructions
476+
let Predicates = [IsISAFuture] in {
477+
def DMSHA2HASH :
478+
XForm_AT3_T1_AB3<31, 14, 177, (outs dmr:$AT), (ins dmr:$ATi, dmr:$AB, u1imm:$T),
479+
"dmsha2hash $AT, $AB, $T",
480+
[(set v1024i1:$AT, (int_ppc_mma_dmsha2hash v1024i1:$ATi, v1024i1:$AB, timm:$T))]>,
481+
RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
482+
483+
def DMSHA3HASH :
484+
XForm_ATp2_SR5<31, 15, 177, (outs dmrprc:$ATp), (ins dmrprc:$ATpi , u5imm:$SR),
485+
"dmsha3hash $ATp, $SR",
486+
[(set v2048i1:$ATp, (int_ppc_mma_dmsha3hash v2048i1:$ATpi, timm:$SR))]>,
487+
RegConstraint<"$ATpi = $ATp">, NoEncode<"$ATpi">;
488+
489+
def DMXXSHAPAD :
490+
XX2Form_AT3_XB6_ID2_E1_BL2<60, 421, (outs dmr:$AT),
491+
(ins dmr:$ATi, vsrc:$XB, u2imm:$ID, u1imm:$E, u2imm:$BL),
492+
"dmxxshapad $AT, $XB, $ID, $E, $BL", []>,
493+
RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
494+
}
495+
418496
// MMA+ Intrinsics
419497
let Predicates = [MMA, IsISAFuture] in {
420498
def : Pat<(v1024i1 (int_ppc_mma_dmxvi8gerx4 v256i1:$XAp, v16i8:$XB)),
@@ -532,3 +610,48 @@ let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
532610
(PMDMXVF16GERX2NN $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
533611
Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
534612
}
613+
614+
// Cryptography Intrinsic
615+
let Predicates = [IsISAFuture] in {
616+
def : Pat<(v1024i1 (int_ppc_mma_dmxxshapad v1024i1:$ATi, v16i8:$XB, timm:$ID,
617+
timm:$E, timm:$BL)), (DMXXSHAPAD $ATi, RCCp.BToVSRC, $ID, $E, $BL)>;
618+
}
619+
620+
// MMA+ Instruction aliases
621+
let Predicates = [IsISAFuture] in {
622+
def : InstAlias<"dmsha256hash $AT, $AB",
623+
(DMSHA2HASH dmr:$AT, dmr:$AB, 0)>;
624+
625+
def : InstAlias<"dmsha512hash $AT, $AB",
626+
(DMSHA2HASH dmr:$AT, dmr:$AB, 1)>;
627+
628+
def : InstAlias<"dmsha3dw $ATp",
629+
(DMSHA3HASH dmrprc:$ATp, 0)>;
630+
631+
def : InstAlias<"dmcryshash $ATp",
632+
(DMSHA3HASH dmrprc:$ATp, 12)>;
633+
634+
def : InstAlias<"dmxxsha3512pad $AT, $XB, $E",
635+
(DMXXSHAPAD dmr:$AT, vsrc:$XB, 0, u1imm:$E, 0)>;
636+
637+
def : InstAlias<"dmxxsha3384pad $AT, $XB, $E",
638+
(DMXXSHAPAD dmr:$AT, vsrc:$XB, 0, u1imm:$E, 1)>;
639+
640+
def : InstAlias<"dmxxsha3256pad $AT, $XB, $E",
641+
(DMXXSHAPAD dmr:$AT, vsrc:$XB, 0, u1imm:$E, 2)>;
642+
643+
def : InstAlias<"dmxxsha3224pad $AT, $XB, $E",
644+
(DMXXSHAPAD dmr:$AT, vsrc:$XB, 0, u1imm:$E, 3)>;
645+
646+
def : InstAlias<"dmxxshake256pad $AT, $XB, $E",
647+
(DMXXSHAPAD dmr:$AT, vsrc:$XB, 1, u1imm:$E, 0)>;
648+
649+
def : InstAlias<"dmxxshake128pad $AT, $XB, $E",
650+
(DMXXSHAPAD dmr:$AT, vsrc:$XB, 1, u1imm:$E, 1)>;
651+
652+
def : InstAlias<"dmxxsha384512pad $AT, $XB",
653+
(DMXXSHAPAD dmr:$AT, vsrc:$XB, 2, 0, 0)>;
654+
655+
def : InstAlias<"dmxxsha224256pad $AT, $XB",
656+
(DMXXSHAPAD dmr:$AT, vsrc:$XB, 3, 0, 0)>;
657+
}

‎llvm/lib/Target/PowerPC/PPCRegisterInfo.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1140,6 +1140,6 @@ def PPCRegDMRpRCAsmOperand : AsmOperandClass {
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let PredicateMethod = "isDMRpRegNumber";
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}
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def dmrp : RegisterOperand<DMRpRC> {
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def dmrprc : RegisterOperand<DMRpRC> {
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let ParserMatchClass = PPCRegDMRpRCAsmOperand;
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}

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