Skip to content

Commit 95c5386

Browse files
lenarylenary
authored
[RISCV][NFCI] Rationalize Immediate Definitions (llvm#120718)
1 parent e138f78 commit 95c5386

File tree

7 files changed

+48
-83
lines changed

7 files changed

+48
-83
lines changed

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -316,6 +316,9 @@ enum OperandType : unsigned {
316316
OPERAND_UIMM11,
317317
OPERAND_UIMM12,
318318
OPERAND_UIMM16,
319+
OPERAND_UIMM20,
320+
OPERAND_UIMMLOG2XLEN,
321+
OPERAND_UIMMLOG2XLEN_NONZERO,
319322
OPERAND_UIMM32,
320323
OPERAND_UIMM48,
321324
OPERAND_UIMM64,
@@ -327,9 +330,6 @@ enum OperandType : unsigned {
327330
OPERAND_SIMM10_LSB0000_NONZERO,
328331
OPERAND_SIMM12,
329332
OPERAND_SIMM12_LSB00000,
330-
OPERAND_UIMM20,
331-
OPERAND_UIMMLOG2XLEN,
332-
OPERAND_UIMMLOG2XLEN_NONZERO,
333333
OPERAND_CLUI_IMM,
334334
OPERAND_VTYPEI10,
335335
OPERAND_VTYPEI11,

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -80,11 +80,11 @@ class RISCVMCCodeEmitter : public MCCodeEmitter {
8080
SmallVectorImpl<MCFixup> &Fixups,
8181
const MCSubtargetInfo &STI) const;
8282

83-
unsigned getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
83+
uint64_t getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
8484
SmallVectorImpl<MCFixup> &Fixups,
8585
const MCSubtargetInfo &STI) const;
8686

87-
unsigned getImmOpValue(const MCInst &MI, unsigned OpNo,
87+
uint64_t getImmOpValue(const MCInst &MI, unsigned OpNo,
8888
SmallVectorImpl<MCFixup> &Fixups,
8989
const MCSubtargetInfo &STI) const;
9090

@@ -385,22 +385,22 @@ RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
385385
return 0;
386386
}
387387

388-
unsigned
388+
uint64_t
389389
RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
390390
SmallVectorImpl<MCFixup> &Fixups,
391391
const MCSubtargetInfo &STI) const {
392392
const MCOperand &MO = MI.getOperand(OpNo);
393393

394394
if (MO.isImm()) {
395-
unsigned Res = MO.getImm();
395+
uint64_t Res = MO.getImm();
396396
assert((Res & 1) == 0 && "LSB is non-zero");
397397
return Res >> 1;
398398
}
399399

400400
return getImmOpValue(MI, OpNo, Fixups, STI);
401401
}
402402

403-
unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
403+
uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
404404
SmallVectorImpl<MCFixup> &Fixups,
405405
const MCSubtargetInfo &STI) const {
406406
bool EnableRelax = STI.hasFeature(RISCV::FeatureRelax);

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2466,6 +2466,10 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
24662466
#define CASE_OPERAND_UIMM(NUM) \
24672467
case RISCVOp::OPERAND_UIMM##NUM: \
24682468
Ok = isUInt<NUM>(Imm); \
2469+
break;
2470+
#define CASE_OPERAND_SIMM(NUM) \
2471+
case RISCVOp::OPERAND_SIMM##NUM: \
2472+
Ok = isInt<NUM>(Imm); \
24692473
break;
24702474
CASE_OPERAND_UIMM(1)
24712475
CASE_OPERAND_UIMM(2)
@@ -2511,15 +2515,14 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
25112515
case RISCVOp::OPERAND_ZERO:
25122516
Ok = Imm == 0;
25132517
break;
2514-
case RISCVOp::OPERAND_SIMM5:
2515-
Ok = isInt<5>(Imm);
2516-
break;
2518+
// clang-format off
2519+
CASE_OPERAND_SIMM(5)
2520+
CASE_OPERAND_SIMM(6)
2521+
CASE_OPERAND_SIMM(12)
2522+
// clang-format on
25172523
case RISCVOp::OPERAND_SIMM5_PLUS1:
25182524
Ok = (isInt<5>(Imm) && Imm != -16) || Imm == 16;
25192525
break;
2520-
case RISCVOp::OPERAND_SIMM6:
2521-
Ok = isInt<6>(Imm);
2522-
break;
25232526
case RISCVOp::OPERAND_SIMM6_NONZERO:
25242527
Ok = Imm != 0 && isInt<6>(Imm);
25252528
break;
@@ -2529,9 +2532,6 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
25292532
case RISCVOp::OPERAND_VTYPEI11:
25302533
Ok = isUInt<11>(Imm);
25312534
break;
2532-
case RISCVOp::OPERAND_SIMM12:
2533-
Ok = isInt<12>(Imm);
2534-
break;
25352535
case RISCVOp::OPERAND_SIMM12_LSB00000:
25362536
Ok = isShiftedInt<7, 5>(Imm);
25372537
break;

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 17 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -159,8 +159,15 @@ class RISCVOp<ValueType vt = XLenVT> : Operand<vt> {
159159

160160
class RISCVUImmOp<int bitsNum> : RISCVOp {
161161
let ParserMatchClass = UImmAsmOperand<bitsNum>;
162+
let EncoderMethod = "getImmOpValue";
162163
let DecoderMethod = "decodeUImmOperand<" # bitsNum # ">";
163164
let OperandType = "OPERAND_UIMM" # bitsNum;
165+
let MCOperandPredicate = [{
166+
int64_t Imm;
167+
if (!MCOp.evaluateAsConstantImm(Imm))
168+
return false;
169+
return isUInt<}]# bitsNum #[{>(Imm);
170+
}];
164171
}
165172

166173
class RISCVUImmLeafOp<int bitsNum> :
@@ -171,6 +178,12 @@ class RISCVSImmOp<int bitsNum> : RISCVOp {
171178
let EncoderMethod = "getImmOpValue";
172179
let DecoderMethod = "decodeSImmOperand<" # bitsNum # ">";
173180
let OperandType = "OPERAND_SIMM" # bitsNum;
181+
let MCOperandPredicate = [{
182+
int64_t Imm;
183+
if (!MCOp.evaluateAsConstantImm(Imm))
184+
return false;
185+
return isInt<}] # bitsNum # [{>(Imm);
186+
}];
174187
}
175188

176189
class RISCVSImmLeafOp<int bitsNum> :
@@ -221,16 +234,9 @@ def InsnDirectiveOpcode : AsmOperandClass {
221234
}
222235

223236
def uimm1 : RISCVUImmLeafOp<1>;
224-
def uimm2 : RISCVUImmLeafOp<2> {
225-
let MCOperandPredicate = [{
226-
int64_t Imm;
227-
if (!MCOp.evaluateAsConstantImm(Imm))
228-
return false;
229-
return isUInt<2>(Imm);
230-
}];
231-
}
237+
def uimm2 : RISCVUImmLeafOp<2>;
232238
def uimm3 : RISCVUImmOp<3>;
233-
def uimm4 : RISCVUImmOp<4>;
239+
def uimm4 : RISCVUImmLeafOp<4>;
234240
def uimm5 : RISCVUImmLeafOp<5>;
235241
def uimm6 : RISCVUImmLeafOp<6>;
236242
def uimm7_opcode : RISCVUImmOp<7> {
@@ -271,13 +277,7 @@ def simm13_lsb0 : Operand<OtherVT> {
271277
let OperandType = "OPERAND_PCREL";
272278
}
273279

274-
class UImm20Operand : RISCVOp {
275-
let EncoderMethod = "getImmOpValue";
276-
let DecoderMethod = "decodeUImmOperand<20>";
277-
let OperandType = "OPERAND_UIMM20";
278-
}
279-
280-
class UImm20OperandMaybeSym : UImm20Operand {
280+
class UImm20OperandMaybeSym : RISCVUImmOp<20> {
281281
let MCOperandPredicate = [{
282282
int64_t Imm;
283283
if (MCOp.evaluateAsConstantImm(Imm))
@@ -293,15 +293,7 @@ def uimm20_auipc : UImm20OperandMaybeSym {
293293
let ParserMatchClass = UImmAsmOperand<20, "AUIPC">;
294294
}
295295

296-
def uimm20 : UImm20Operand {
297-
let ParserMatchClass = UImmAsmOperand<20>;
298-
let MCOperandPredicate = [{
299-
int64_t Imm;
300-
if (!MCOp.evaluateAsConstantImm(Imm))
301-
return false;
302-
return isUInt<20>(Imm);
303-
}];
304-
}
296+
def uimm20 : RISCVUImmOp<20>;
305297

306298
def Simm21Lsb0JALAsmOperand : SImmAsmOperand<21, "Lsb0JAL"> {
307299
let ParserMethod = "parseJALOffset";

‎llvm/lib/Target/RISCV/RISCVInstrInfoC.td

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -151,7 +151,6 @@ def simm9_lsb0 : Operand<OtherVT>,
151151
if (MCOp.evaluateAsConstantImm(Imm))
152152
return isShiftedInt<8, 1>(Imm);
153153
return MCOp.isBareSymbolRef();
154-
155154
}];
156155
let OperandType = "OPERAND_PCREL";
157156
}
@@ -227,10 +226,8 @@ def InsnCDirectiveOpcode : AsmOperandClass {
227226
let PredicateMethod = "isImm";
228227
}
229228

230-
def uimm2_opcode : RISCVOp {
229+
def uimm2_opcode : RISCVUImmOp<2> {
231230
let ParserMatchClass = InsnCDirectiveOpcode;
232-
let DecoderMethod = "decodeUImmOperand<2>";
233-
let OperandType = "OPERAND_UIMM2";
234231
}
235232

236233
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfoV.td

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -66,15 +66,9 @@ def simm5 : RISCVSImmLeafOp<5> {
6666
}];
6767
}
6868

69-
def SImm5Plus1AsmOperand : AsmOperandClass {
70-
let Name = "SImm5Plus1";
71-
let RenderMethod = "addImmOperands";
72-
let DiagnosticType = "InvalidSImm5Plus1";
73-
}
74-
7569
def simm5_plus1 : RISCVOp, ImmLeaf<XLenVT,
7670
[{return (isInt<5>(Imm) && Imm != -16) || Imm == 16;}]> {
77-
let ParserMatchClass = SImm5Plus1AsmOperand;
71+
let ParserMatchClass = SImmAsmOperand<5, "Plus1">;
7872
let OperandType = "OPERAND_SIMM5_PLUS1";
7973
let MCOperandPredicate = [{
8074
int64_t Imm;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXwch.td

Lines changed: 12 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -25,24 +25,6 @@ class QKStackInst<bits<2> funct2, dag outs, dag ins,
2525
// Operand definitions.
2626
//===----------------------------------------------------------------------===//
2727

28-
def uimm4_with_predicate : RISCVUImmLeafOp<4> {
29-
let MCOperandPredicate = [{
30-
int64_t Imm;
31-
if (!MCOp.evaluateAsConstantImm(Imm))
32-
return false;
33-
return isUInt<4>(Imm);
34-
}];
35-
}
36-
37-
def uimm5_with_predicate : RISCVUImmLeafOp<5> {
38-
let MCOperandPredicate = [{
39-
int64_t Imm;
40-
if (!MCOp.evaluateAsConstantImm(Imm))
41-
return false;
42-
return isUInt<5>(Imm);
43-
}];
44-
}
45-
4628
// A 5-bit unsigned immediate where the least significant bit is zero.
4729
def uimm5_lsb0 : RISCVOp,
4830
ImmLeaf<XLenVT, [{return isShiftedUInt<4, 1>(Imm);}]> {
@@ -80,7 +62,7 @@ let Predicates = [HasVendorXwchc], DecoderNamespace = "Xwchc" in {
8062

8163
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
8264
def QK_C_LBU : RVInst16CL<0b001, 0b00, (outs GPRC:$rd),
83-
(ins GPRCMem:$rs1, uimm5_with_predicate:$imm),
65+
(ins GPRCMem:$rs1, uimm5:$imm),
8466
"qk.c.lbu", "$rd, ${imm}(${rs1})">,
8567
Sched<[WriteLDB, ReadMemBase]> {
8668
bits<5> imm;
@@ -91,7 +73,7 @@ def QK_C_LBU : RVInst16CL<0b001, 0b00, (outs GPRC:$rd),
9173
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
9274
def QK_C_SB : RVInst16CS<0b101, 0b00, (outs),
9375
(ins GPRC:$rs2, GPRCMem:$rs1,
94-
uimm5_with_predicate:$imm),
76+
uimm5:$imm),
9577
"qk.c.sb", "$rs2, ${imm}(${rs1})">,
9678
Sched<[WriteSTB, ReadStoreData, ReadMemBase]> {
9779
bits<5> imm;
@@ -121,7 +103,7 @@ def QK_C_SH : RVInst16CS<0b101, 0b10, (outs),
121103

122104
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
123105
def QK_C_LBUSP : QKStackInst<0b00, (outs GPRC:$rd_rs2),
124-
(ins SPMem:$rs1, uimm4_with_predicate:$imm),
106+
(ins SPMem:$rs1, uimm4:$imm),
125107
"qk.c.lbusp", "$rd_rs2, ${imm}(${rs1})">,
126108
Sched<[WriteLDB, ReadMemBase]> {
127109
bits<4> imm;
@@ -130,7 +112,7 @@ def QK_C_LBUSP : QKStackInst<0b00, (outs GPRC:$rd_rs2),
130112
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
131113
def QK_C_SBSP : QKStackInst<0b10, (outs),
132114
(ins GPRC:$rd_rs2, SPMem:$rs1,
133-
uimm4_with_predicate:$imm),
115+
uimm4:$imm),
134116
"qk.c.sbsp", "$rd_rs2, ${imm}(${rs1})">,
135117
Sched<[WriteSTB, ReadStoreData, ReadMemBase]> {
136118
bits<4> imm;
@@ -180,18 +162,18 @@ def : InstAlias<"qk.c.shsp $rs2, (${rs1})", (QK_C_SHSP GPRC:$rs2, SPMem:$rs1, 0)
180162
//===----------------------------------------------------------------------===//
181163

182164
let Predicates = [HasVendorXwchc] in {
183-
def : CompressPat<(LBU GPRC:$rd, GPRCMem:$rs1, uimm5_with_predicate:$imm),
184-
(QK_C_LBU GPRC:$rd, GPRCMem:$rs1, uimm5_with_predicate:$imm)>;
185-
def : CompressPat<(SB GPRC:$rs2, GPRCMem:$rs1, uimm5_with_predicate:$imm),
186-
(QK_C_SB GPRC:$rs2, GPRCMem:$rs1, uimm5_with_predicate:$imm)>;
165+
def : CompressPat<(LBU GPRC:$rd, GPRCMem:$rs1, uimm5:$imm),
166+
(QK_C_LBU GPRC:$rd, GPRCMem:$rs1, uimm5:$imm)>;
167+
def : CompressPat<(SB GPRC:$rs2, GPRCMem:$rs1, uimm5:$imm),
168+
(QK_C_SB GPRC:$rs2, GPRCMem:$rs1, uimm5:$imm)>;
187169
def : CompressPat<(LHU GPRC:$rd, GPRCMem:$rs1, uimm6_lsb0:$imm),
188170
(QK_C_LHU GPRC:$rd, GPRCMem:$rs1, uimm6_lsb0:$imm)>;
189171
def : CompressPat<(SH GPRC:$rs2, GPRCMem:$rs1, uimm6_lsb0:$imm),
190172
(QK_C_SH GPRC:$rs2, GPRCMem:$rs1, uimm6_lsb0:$imm)>;
191-
def : CompressPat<(LBU GPRC:$rd, SPMem:$rs1, uimm4_with_predicate:$imm),
192-
(QK_C_LBUSP GPRC:$rd, SPMem:$rs1, uimm4_with_predicate:$imm)>;
193-
def : CompressPat<(SB GPRC:$rs2, SPMem:$rs1, uimm4_with_predicate:$imm),
194-
(QK_C_SBSP GPRC:$rs2, SPMem:$rs1, uimm4_with_predicate:$imm)>;
173+
def : CompressPat<(LBU GPRC:$rd, SPMem:$rs1, uimm4:$imm),
174+
(QK_C_LBUSP GPRC:$rd, SPMem:$rs1, uimm4:$imm)>;
175+
def : CompressPat<(SB GPRC:$rs2, SPMem:$rs1, uimm4:$imm),
176+
(QK_C_SBSP GPRC:$rs2, SPMem:$rs1, uimm4:$imm)>;
195177
def : CompressPat<(LHU GPRC:$rd, SPMem:$rs1, uimm5_lsb0:$imm),
196178
(QK_C_LHUSP GPRC:$rd, SPMem:$rs1, uimm5_lsb0:$imm)>;
197179
def : CompressPat<(SH GPRC:$rs2, SPMem:$rs1, uimm5_lsb0:$imm),

0 commit comments

Comments
 (0)