[HeterogeneousDwarf] Thread-focus vector registers in AsmPrinter (llvm#765)

epilk · web-flow · commit 845edee678a1 · 2025-02-24T09:18:21.000-05:00
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -1111,6 +1111,14 @@ class TargetRegisterInfo : public MCRegisterInfo {
   prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags,
                           const StackOffset &Offset) const;
 
+  /// If the register corresponding to DwarfReg is a vector register that holds
+  /// a per-thread value in each lane, return the size in bytes of the lane.
+  /// Otherwise return nullopt.
+  virtual std::optional<unsigned> getDwarfRegLaneSize(int64_t DwarfReg,
+                                                      bool isEH) const {
+    return std::nullopt;
+  }
+
   /// Spill the register so it can be used by the register scavenger.
   /// Return true if the register was spilled, false otherwise.
   /// If this function does not spill the register, the scavenger
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
@@ -951,7 +951,7 @@ std::optional<NewOpResult> DwarfExpression::traverse(DIOp::Arg Arg,
 
   if (Entry.isLocation()) {
     assert(DwarfRegs.empty() && "unconsumed registers?");
-    if (!addMachineReg(*TRI, Entry.getLoc().getReg())) {
+    if (!TRI || !addMachineReg(*TRI, Entry.getLoc().getReg())) {
       DwarfRegs.clear();
       return std::nullopt;
     }
@@ -968,8 +968,19 @@ std::optional<NewOpResult> DwarfExpression::traverse(DIOp::Arg Arg,
     SubRegOffset /= 8;
     SubRegSize /= 8;
 
+    auto focusThreadIfRequired = [this](int64_t DwarfRegNo) {
+      // FIXME: This should be represented in the DIExpression.
+      if (auto LaneSize = TRI->getDwarfRegLaneSize(DwarfRegNo, false)) {
+        emitUserOp(dwarf::DW_OP_LLVM_USER_push_lane);
+        emitConstu(*LaneSize);
+        emitOp(dwarf::DW_OP_mul);
+        emitUserOp(dwarf::DW_OP_LLVM_USER_offset);
+      }
+    };
+
     if (Regs.size() == 1) {
       addReg(Regs[0].DwarfRegNo, Regs[0].Comment);
+      focusThreadIfRequired(Regs[0].DwarfRegNo);
 
       if (SubRegOffset) {
         emitUserOp(dwarf::DW_OP_LLVM_USER_offset_uconst);
@@ -994,8 +1005,10 @@ std::optional<NewOpResult> DwarfExpression::traverse(DIOp::Arg Arg,
     for (auto &Reg : Regs) {
       if (Reg.SubRegSize % 8)
         return std::nullopt;
-      if (Reg.DwarfRegNo >= 0)
+      if (Reg.DwarfRegNo >= 0) {
         addReg(Reg.DwarfRegNo, Reg.Comment);
+        focusThreadIfRequired(Regs[0].DwarfRegNo);
+      }
       emitOp(dwarf::DW_OP_piece);
       emitUnsigned(Reg.SubRegSize / 8);
     }
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1139,6 +1139,16 @@ bool SIRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
                                 SIInstrFlags::FlatScratch);
 }
 
+std::optional<unsigned> SIRegisterInfo::getDwarfRegLaneSize(int64_t DwarfReg,
+                                                            bool IsEH) const {
+  if (std::optional<MCRegister> Reg = getLLVMRegNum(DwarfReg, IsEH)) {
+    const TargetRegisterClass *RC = getPhysRegBaseClass(*Reg);
+    if (RC == &AMDGPU::VGPR_32RegClass || RC == &AMDGPU::AGPR_32RegClass)
+      return 4;
+  }
+  return std::nullopt;
+}
+
 const TargetRegisterClass *SIRegisterInfo::getPointerRegClass(
   const MachineFunction &MF, unsigned Kind) const {
   // This is inaccurate. It depends on the instruction and address space. The
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -143,6 +143,9 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
   bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
                           int64_t Offset) const override;
 
+  std::optional<unsigned> getDwarfRegLaneSize(int64_t DwarfReg,
+                                              bool isEH) const override;
+
   const TargetRegisterClass *getPointerRegClass(
     const MachineFunction &MF, unsigned Kind = 0) const override;
 
diff --git a/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-diexpression-args.ll b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-diexpression-args.ll
@@ -25,7 +25,7 @@ define amdgpu_kernel void @int64_k(i64 %a) !dbg !31 {
 ; CHECK-LABEL: DW_AT_name ("as1_ptr")
 define void @as1_ptr(ptr addrspace(1) %ptr) !dbg !16 {
   ; CHECK: DW_AT_location
-  ; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_piece 0x4, DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_piece 0x4)
+  ; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4)
   tail call void @llvm.dbg.value(metadata ptr addrspace(1) %ptr, metadata !17, metadata !DIExpression(DIOpArg(0, ptr addrspace(1)))), !dbg !20
   store ptr addrspace(1) %ptr, ptr @glob_ptr, align 8, !dbg !20
   ret void, !dbg !20
@@ -34,15 +34,15 @@ define void @as1_ptr(ptr addrspace(1) %ptr) !dbg !16 {
 ; CHECK-LABEL: DW_AT_name ("int64")
 define void @int64(i64 %a) !dbg !21 {
   ; CHECK: DW_AT_location
-  ; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_piece 0x4, DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_piece 0x4)
+  ; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4)
   tail call void @llvm.dbg.value(metadata i64 %a, metadata !22, metadata !DIExpression(DIOpArg(0, i64))), !dbg !23
   store i64 %a, ptr @glob_ptr, align 8, !dbg !23
   ret void, !dbg !24
 }
 
 ; CHECK-LABEL: DW_AT_name ("int32")
 define void @int32(i32 %a) !dbg !25 {
-  ; CHECK: DW_AT_location (DW_OP_regx 0x{{[0-9a-z]+}})
+  ; CHECK: DW_AT_location (DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset)
   tail call void @llvm.dbg.value(metadata i32 %a, metadata !26, metadata !DIExpression(DIOpArg(0, i32))), !dbg !27
   store i32 %a, ptr @glob_ptr, align 4, !dbg !27
   ret void, !dbg !27
@@ -51,7 +51,7 @@ define void @int32(i32 %a) !dbg !25 {
 ; CHECK-LABEL: DW_AT_name ("gen_ptr")
 define void @gen_ptr(ptr %ptr) !dbg !28 {
   ; CHECK: DW_AT_location
-  ; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_piece 0x4, DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_piece 0x4)
+  ; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4)
   tail call void @llvm.dbg.value(metadata ptr %ptr, metadata !29, metadata !DIExpression(DIOpArg(0, ptr))), !dbg !30
   store ptr %ptr, ptr @glob_ptr, align 8, !dbg !30
   ret void, !dbg !30
diff --git a/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-diexpression-subregs.mir b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-diexpression-subregs.mir
@@ -7,7 +7,7 @@
   define void @kern() #0 !dbg !9 {
     ret void, !dbg !16
   }
-  attributes #0 = { convergent mustprogress noinline nounwind optnone "amdgpu-stack-objects" "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx900" "target-features"="+16-bit-insts,+ci-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst" "uniform-work-group-size"="false" }
+  attributes #0 = { noinline optnone }
 
   !llvm.dbg.cu = !{!0}
   !llvm.module.flags = !{!2, !3, !4, !5, !6, !7}
@@ -39,6 +39,7 @@
   !23 = !DILocalVariable(name: "with_frags", scope: !9, file: !1, line: 1, type: !15)
   !24 = !DILocalVariable(name: "sgpr", scope: !9, file: !1, line: 1, type: !14)
   !25 = !DILocalVariable(name: "vgpr", scope: !9, file: !1, line: 1, type: !14)
+  !26 = !DILocalVariable(name: "vgpr_frags", scope: !9, file: !1, line: 1, type: !15)
 
 ...
 ---
@@ -58,15 +59,15 @@ body: |
     ; CHECK-NEXT: DW_AT_name ("s_s")
     DBG_VALUE renamable $sgpr42_sgpr43, $noreg, !19, !DIExpression(DIOpArg(0, i64)), debug-location !16
 
-    ; CHECK: DW_AT_location (DW_OP_regx VGPR42)
+    ; CHECK: DW_AT_location (DW_OP_regx VGPR42, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset)
     ; CHECK-NEXT: DW_AT_name ("v_lo16")
     DBG_VALUE renamable $vgpr42_lo16, $noreg, !20, !DIExpression(DIOpArg(0, i16)), debug-location !16
 
-    ; CHECK: DW_AT_location (DW_OP_regx VGPR42, DW_OP_LLVM_user DW_OP_LLVM_offset_uconst 0x2)
+    ; CHECK: DW_AT_location (DW_OP_regx VGPR42, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_LLVM_user DW_OP_LLVM_offset_uconst 0x2)
     ; CHECK-NEXT: DW_AT_name ("v_hi16")
     DBG_VALUE renamable $vgpr42_hi16, $noreg, !21, !DIExpression(DIOpArg(0, i16)), debug-location !16
 
-    ; CHECK: DW_AT_location (DW_OP_regx VGPR42, DW_OP_piece 0x4, DW_OP_regx VGPR43, DW_OP_piece 0x4, DW_OP_LLVM_user DW_OP_LLVM_piece_end)
+    ; CHECK: DW_AT_location (DW_OP_regx VGPR42, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_regx VGPR43, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_LLVM_user DW_OP_LLVM_piece_end)
     ; CHECK-NEXT: DW_AT_name ("v_v")
     DBG_VALUE renamable $vgpr42_vgpr43, $noreg, !22, !DIExpression(DIOpArg(0, i64)), debug-location !16
 
@@ -81,10 +82,17 @@ body: |
     ; CHECK-NEXT: DW_AT_name ("sgpr")
     DBG_VALUE $sgpr100, $noreg, !24, !DIExpression(DIOpArg(0, i32)), debug-location !16
 
-    ; CHECK: DW_AT_location (DW_OP_regx VGPR100)
+    ; CHECK: DW_AT_location (DW_OP_regx VGPR100, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset)
     ; CHECK-NEXT: ("vgpr")
     DBG_VALUE $vgpr100, $noreg, !25, !DIExpression(DIOpArg(0, i32)), debug-location !16
 
+    ; CHECK: DW_TAG_variable
+    ; CHECK-NEXT: DW_AT_location (indexed ({{.*}}) loclist = {{.*}}:
+    ; CHECK-NEXT:   [{{.*}}): DW_OP_lit0, DW_OP_regx VGPR42, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_regx VGPR43, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_LLVM_user DW_OP_LLVM_piece_end, DW_OP_swap, DW_OP_drop, DW_OP_piece 0x4, DW_OP_lit0, DW_OP_regx VGPR44, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_regx VGPR45, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_LLVM_user DW_OP_LLVM_piece_end, DW_OP_swap, DW_OP_drop, DW_OP_piece 0x4)
+    ; CHECK-NEXT: DW_AT_name    ("vgpr_frags")
+    DBG_VALUE renamable $vgpr42_vgpr43, $noreg, !26, !DIExpression(DIOpArg(0, i64), DIOpFragment(0, 32)), debug-location !16
+    DBG_VALUE renamable $vgpr44_vgpr45, $noreg, !26, !DIExpression(DIOpArg(0, i64), DIOpFragment(32, 32)), debug-location !16
+
     S_ENDPGM 0, debug-location !16
 
 ...
diff --git a/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-frags.mir b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-frags.mir
@@ -55,18 +55,18 @@ body: |
 
 
     ; CHECK: DW_AT_location
-    ; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_piece 0x2, DW_OP_regx VGPR44, DW_OP_piece 0x4, DW_OP_regx VGPR45, DW_OP_piece 0x2
+    ; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_piece 0x2, DW_OP_regx VGPR44, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_regx VGPR45, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x2
     DBG_VALUE renamable $vgpr43, $noreg, !18, !DIExpression(DW_OP_LLVM_poisoned, DW_OP_LLVM_fragment, 0, 32), debug-location !14
     DBG_VALUE renamable $vgpr44, $noreg, !18, !DIExpression(DIOpArg(0, i32), DIOpFragment(16, 32)), debug-location !14
     DBG_VALUE renamable $vgpr45, $noreg, !18, !DIExpression(DIOpArg(0, i32), DIOpFragment(48, 16)), debug-location !14
     S_NOP 0, debug-location !14
 
-    ; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx VGPR46, DW_OP_piece 0x1, DW_OP_piece 0x1, DW_OP_LLVM_user DW_OP_LLVM_undefined, DW_OP_piece 0x2, DW_OP_piece 0x2, DW_OP_regx VGPR45, DW_OP_piece 0x2
+    ; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx VGPR46, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x1, DW_OP_piece 0x1, DW_OP_LLVM_user DW_OP_LLVM_undefined, DW_OP_piece 0x2, DW_OP_piece 0x2, DW_OP_regx VGPR45, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x2
     DBG_VALUE renamable $vgpr46, $noreg, !18, !DIExpression(DIOpArg(0, i32), DIOpFragment(0, 8)), debug-location !15
     DBG_VALUE renamable $vgpr47, $noreg, !18, !DIExpression(DW_OP_LLVM_poisoned, DW_OP_LLVM_fragment, 16, 16), debug-location !15
     S_NOP 0, debug-location !15
 
-    ; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx VGPR46, DW_OP_piece 0x1, DW_OP_LLVM_user DW_OP_LLVM_undefined, DW_OP_piece 0x7
+    ; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx VGPR46, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x1, DW_OP_LLVM_user DW_OP_LLVM_undefined, DW_OP_piece 0x7
     ; CHECK-NEXT: DW_AT_name ("overlaps")
     DBG_VALUE renamable $vgpr48, $noreg, !18, !DIExpression(DW_OP_LLVM_poisoned, DW_OP_LLVM_fragment, 8, 56), debug-location !16
 
