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[SPIR-V] Add SPV_INTEL_memory_access_aliasing extension (llvm#129800)
Spec can be found here intel/llvm#15225 TODO for future patches: - During spec review need to decide whether only FunctionCall or Atomic instructions can be decorated and if not - move the code around adding handling for other instructions; - Handle optional string metadata; - Handle LLVM atomic instructions; - Handle SPIR-V friendly atomic calls returning via sret argument. Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>
1 parent 0ce4b68 commit 7a44ff1

22 files changed

+495
-11
lines changed

‎llvm/docs/SPIRVUsage.rst

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@@ -173,6 +173,8 @@ list of supported SPIR-V extensions, sorted alphabetically by their extension na
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- Adds decorations that can be applied to global (module scope) variables to help code generation for FPGA devices.
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* - ``SPV_INTEL_media_block_io``
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- Adds additional subgroup block read and write functionality that allow applications to flexibly specify the width and height of the block to read from or write to a 2D image.
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* - ``SPV_INTEL_memory_access_aliasing``
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- Adds instructions and decorations to specify memory access aliasing, similar to alias.scope and noalias LLVM metadata.
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* - ``SPV_INTEL_optnone``
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- Adds OptNoneINTEL value for Function Control mask that indicates a request to not optimize the function.
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* - ``SPV_INTEL_split_barrier``
@@ -301,6 +303,10 @@ SPIR-V backend, along with their descriptions and argument details.
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- None
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- `[Type, Metadata]`
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- Assigns decoration to values by associating them with metadatas. Not emitted directly but used to support SPIR-V representation in LLVM IR.
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* - `int_spv_assign_aliasing_decoration`
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- None
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- `[Type, 32-bit Integer, Metadata]`
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- Assigns one of two memory aliasing decorations (specified by the second argument) to instructions using original aliasing metadata node. Not emitted directly but used to support SPIR-V representation in LLVM IR.
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* - `int_spv_track_constant`
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- Type
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- `[Type, Metadata]`

‎llvm/include/llvm/IR/IntrinsicsSPIRV.td

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@@ -138,4 +138,7 @@ let TargetPrefix = "spv" in {
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def int_spv_resource_store_typedbuffer
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: DefaultAttrsIntrinsic<[], [llvm_any_ty, llvm_i32_ty, llvm_anyvector_ty]>;
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// Memory aliasing intrinsics
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def int_spv_assign_aliasing_decoration : Intrinsic<[], [llvm_any_ty, llvm_i32_ty, llvm_metadata_ty], [ImmArg<ArgIndex<1>>]>;
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}

‎llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp

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@@ -611,6 +611,9 @@ void SPIRVAsmPrinter::outputModuleSections() {
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outputModuleSection(SPIRV::MB_DebugNames);
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// 7c. Debug: all OpModuleProcessed instructions.
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outputModuleSection(SPIRV::MB_DebugModuleProcessed);
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// xxx. SPV_INTEL_memory_access_aliasing instructions go before 8.
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// "All annotation instructions"
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outputModuleSection(SPIRV::MB_AliasingInsts);
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// 8. All annotation instructions (all decorations).
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outputAnnotations(*M);
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// 9. All type declarations (OpTypeXXX instructions), all constant

‎llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp

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@@ -695,6 +695,20 @@ bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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return false;
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MIB.addUse(Arg.Regs[0]);
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}
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if (ST->canUseExtension(SPIRV::Extension::SPV_INTEL_memory_access_aliasing)) {
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// Process aliasing metadata.
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const CallBase *CI = Info.CB;
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if (CI && CI->hasMetadata()) {
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if (MDNode *MD = CI->getMetadata(LLVMContext::MD_alias_scope))
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GR->buildMemAliasingOpDecorate(ResVReg, MIRBuilder,
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SPIRV::Decoration::AliasScopeINTEL, MD);
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if (MDNode *MD = CI->getMetadata(LLVMContext::MD_noalias))
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GR->buildMemAliasingOpDecorate(ResVReg, MIRBuilder,
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SPIRV::Decoration::NoAliasINTEL, MD);
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}
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}
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return MIB.constrainAllUses(MIRBuilder.getTII(), *ST->getRegisterInfo(),
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*ST->getRegBankInfo());
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}

‎llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp

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@@ -53,6 +53,8 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
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SPIRV::Extension::Extension::SPV_INTEL_subgroups},
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{"SPV_INTEL_media_block_io",
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SPIRV::Extension::Extension::SPV_INTEL_media_block_io},
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{"SPV_INTEL_memory_access_aliasing",
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SPIRV::Extension::Extension::SPV_INTEL_memory_access_aliasing},
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{"SPV_INTEL_joint_matrix",
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SPIRV::Extension::Extension::SPV_INTEL_joint_matrix},
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{"SPV_KHR_uniform_group_instructions",

‎llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp

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@@ -151,6 +151,7 @@ class SPIRVEmitIntrinsics
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unsigned OperandToReplace,
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IRBuilder<> &B);
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void insertPtrCastOrAssignTypeInstr(Instruction *I, IRBuilder<> &B);
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bool shouldTryToAddMemAliasingDecoration(Instruction *Inst);
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void insertSpirvDecorations(Instruction *I, IRBuilder<> &B);
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void processGlobalValue(GlobalVariable &GV, IRBuilder<> &B);
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void processParamTypes(Function *F, IRBuilder<> &B);
@@ -1169,6 +1170,7 @@ void SPIRVEmitIntrinsics::replaceMemInstrUses(Instruction *Old,
11691170
llvm_unreachable("illegal aggregate intrinsic user");
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}
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}
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New->copyMetadata(*Old);
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Old->eraseFromParent();
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}
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@@ -1752,6 +1754,7 @@ Instruction *SPIRVEmitIntrinsics::visitStoreInst(StoreInst &I) {
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Intrinsic::spv_store, {I.getValueOperand()->getType(), PtrOp->getType()},
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{I.getValueOperand(), PtrOp, B.getInt16(Flags),
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B.getInt8(I.getAlign().value())});
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NewI->copyMetadata(I);
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I.eraseFromParent();
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return NewI;
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}
@@ -1955,13 +1958,64 @@ void SPIRVEmitIntrinsics::insertAssignTypeIntrs(Instruction *I,
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}
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}
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bool SPIRVEmitIntrinsics::shouldTryToAddMemAliasingDecoration(
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Instruction *Inst) {
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const SPIRVSubtarget *STI = TM->getSubtargetImpl(*Inst->getFunction());
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if (!STI->canUseExtension(SPIRV::Extension::SPV_INTEL_memory_access_aliasing))
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return false;
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// Add aliasing decorations to internal load and store intrinsics
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// and atomic instructions, skipping atomic store as it won't have ID to
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// attach the decoration.
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CallInst *CI = dyn_cast<CallInst>(Inst);
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if (!CI)
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return false;
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if (Function *Fun = CI->getCalledFunction()) {
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if (Fun->isIntrinsic()) {
1974+
switch (Fun->getIntrinsicID()) {
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case Intrinsic::spv_load:
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case Intrinsic::spv_store:
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return true;
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default:
1979+
return false;
1980+
}
1981+
}
1982+
std::string Name = getOclOrSpirvBuiltinDemangledName(Fun->getName());
1983+
const std::string Prefix = "__spirv_Atomic";
1984+
const bool IsAtomic = Name.find(Prefix) == 0;
1985+
1986+
if (!Fun->getReturnType()->isVoidTy() && IsAtomic)
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return true;
1988+
}
1989+
return false;
1990+
}
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void SPIRVEmitIntrinsics::insertSpirvDecorations(Instruction *I,
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IRBuilder<> &B) {
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if (MDNode *MD = I->getMetadata("spirv.Decorations")) {
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setInsertPointAfterDef(B, I);
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B.CreateIntrinsic(Intrinsic::spv_assign_decoration, {I->getType()},
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{I, MetadataAsValue::get(I->getContext(), MD)});
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}
1999+
// Lower alias.scope/noalias metadata
2000+
{
2001+
auto processMemAliasingDecoration = [&](unsigned Kind) {
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if (MDNode *AliasListMD = I->getMetadata(Kind)) {
2003+
if (shouldTryToAddMemAliasingDecoration(I)) {
2004+
uint32_t Dec = Kind == LLVMContext::MD_alias_scope
2005+
? SPIRV::Decoration::AliasScopeINTEL
2006+
: SPIRV::Decoration::NoAliasINTEL;
2007+
SmallVector<Value *, 3> Args = {
2008+
I, ConstantInt::get(B.getInt32Ty(), Dec),
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MetadataAsValue::get(I->getContext(), AliasListMD)};
2010+
setInsertPointAfterDef(B, I);
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B.CreateIntrinsic(Intrinsic::spv_assign_aliasing_decoration,
2012+
{I->getType()}, {Args});
2013+
}
2014+
}
2015+
};
2016+
processMemAliasingDecoration(LLVMContext::MD_alias_scope);
2017+
processMemAliasingDecoration(LLVMContext::MD_noalias);
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}
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}
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void SPIRVEmitIntrinsics::processInstrAfterVisit(Instruction *I,

‎llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp

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@@ -1759,6 +1759,75 @@ LLT SPIRVGlobalRegistry::getRegType(SPIRVType *SpvType) const {
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return LLT::scalar(64);
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}
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// Aliasing list MD contains several scope MD nodes whithin it. Each scope MD
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// has a selfreference and an extra MD node for aliasing domain and also it
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// can contain an optional string operand. Domain MD contains a self-reference
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// with an optional string operand. Here we unfold the list, creating SPIR-V
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// aliasing instructions.
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// TODO: add support for an optional string operand.
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MachineInstr *SPIRVGlobalRegistry::getOrAddMemAliasingINTELInst(
1769+
MachineIRBuilder &MIRBuilder, const MDNode *AliasingListMD) {
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if (AliasingListMD->getNumOperands() == 0)
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return nullptr;
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if (auto L = AliasInstMDMap.find(AliasingListMD); L != AliasInstMDMap.end())
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return L->second;
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1775+
SmallVector<MachineInstr *> ScopeList;
1776+
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
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for (const MDOperand &MDListOp : AliasingListMD->operands()) {
1778+
if (MDNode *ScopeMD = dyn_cast<MDNode>(MDListOp)) {
1779+
if (ScopeMD->getNumOperands() < 2)
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return nullptr;
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MDNode *DomainMD = dyn_cast<MDNode>(ScopeMD->getOperand(1));
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if (!DomainMD)
1783+
return nullptr;
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auto *Domain = [&] {
1785+
auto D = AliasInstMDMap.find(DomainMD);
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if (D != AliasInstMDMap.end())
1787+
return D->second;
1788+
const Register Ret = MRI->createVirtualRegister(&SPIRV::IDRegClass);
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auto MIB =
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MIRBuilder.buildInstr(SPIRV::OpAliasDomainDeclINTEL).addDef(Ret);
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return MIB.getInstr();
1792+
}();
1793+
AliasInstMDMap.insert(std::make_pair(DomainMD, Domain));
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auto *Scope = [&] {
1795+
auto S = AliasInstMDMap.find(ScopeMD);
1796+
if (S != AliasInstMDMap.end())
1797+
return S->second;
1798+
const Register Ret = MRI->createVirtualRegister(&SPIRV::IDRegClass);
1799+
auto MIB = MIRBuilder.buildInstr(SPIRV::OpAliasScopeDeclINTEL)
1800+
.addDef(Ret)
1801+
.addUse(Domain->getOperand(0).getReg());
1802+
return MIB.getInstr();
1803+
}();
1804+
AliasInstMDMap.insert(std::make_pair(ScopeMD, Scope));
1805+
ScopeList.push_back(Scope);
1806+
}
1807+
}
1808+
1809+
const Register Ret = MRI->createVirtualRegister(&SPIRV::IDRegClass);
1810+
auto MIB =
1811+
MIRBuilder.buildInstr(SPIRV::OpAliasScopeListDeclINTEL).addDef(Ret);
1812+
for (auto *Scope : ScopeList)
1813+
MIB.addUse(Scope->getOperand(0).getReg());
1814+
auto List = MIB.getInstr();
1815+
AliasInstMDMap.insert(std::make_pair(AliasingListMD, List));
1816+
return List;
1817+
}
1818+
1819+
void SPIRVGlobalRegistry::buildMemAliasingOpDecorate(
1820+
Register Reg, MachineIRBuilder &MIRBuilder, uint32_t Dec,
1821+
const MDNode *AliasingListMD) {
1822+
MachineInstr *AliasList =
1823+
getOrAddMemAliasingINTELInst(MIRBuilder, AliasingListMD);
1824+
if (!AliasList)
1825+
return;
1826+
MIRBuilder.buildInstr(SPIRV::OpDecorate)
1827+
.addUse(Reg)
1828+
.addImm(Dec)
1829+
.addUse(AliasList->getOperand(0).getReg());
1830+
}
17621831
void SPIRVGlobalRegistry::replaceAllUsesWith(Value *Old, Value *New,
17631832
bool DeleteOld) {
17641833
Old->replaceAllUsesWith(New);

‎llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h

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@@ -92,6 +92,9 @@ class SPIRVGlobalRegistry {
9292
// Maps OpVariable and OpFunction-related v-regs to its LLVM IR definition.
9393
DenseMap<std::pair<const MachineFunction *, Register>, const Value *> Reg2GO;
9494

95+
// map of aliasing decorations to aliasing metadata
96+
std::unordered_map<const MDNode *, MachineInstr *> AliasInstMDMap;
97+
9598
// Add a new OpTypeXXX instruction without checking for duplicates.
9699
SPIRVType *createSPIRVType(const Type *Type, MachineIRBuilder &MIRBuilder,
97100
SPIRV::AccessQualifier::AccessQualifier AQ,
@@ -621,6 +624,10 @@ class SPIRVGlobalRegistry {
621624
const TargetRegisterClass *getRegClass(SPIRVType *SpvType) const;
622625
LLT getRegType(SPIRVType *SpvType) const;
623626

627+
MachineInstr *getOrAddMemAliasingINTELInst(MachineIRBuilder &MIRBuilder,
628+
const MDNode *AliasingListMD);
629+
void buildMemAliasingOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder,
630+
uint32_t Dec, const MDNode *GVarMD);
624631
// Replace all uses of a |Old| with |New| updates the global registry type
625632
// mappings.
626633
void replaceAllUsesWith(Value *Old, Value *New, bool DeleteOld = true);

‎llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp

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@@ -97,6 +97,17 @@ bool SPIRVInstrInfo::isDecorationInstr(const MachineInstr &MI) const {
9797
}
9898
}
9999

100+
bool SPIRVInstrInfo::isAliasingInstr(const MachineInstr &MI) const {
101+
switch (MI.getOpcode()) {
102+
case SPIRV::OpAliasDomainDeclINTEL:
103+
case SPIRV::OpAliasScopeDeclINTEL:
104+
case SPIRV::OpAliasScopeListDeclINTEL:
105+
return true;
106+
default:
107+
return false;
108+
}
109+
}
110+
100111
bool SPIRVInstrInfo::isHeaderInstr(const MachineInstr &MI) const {
101112
switch (MI.getOpcode()) {
102113
case SPIRV::OpCapability:
@@ -115,7 +126,8 @@ bool SPIRVInstrInfo::isHeaderInstr(const MachineInstr &MI) const {
115126
case SPIRV::OpModuleProcessed:
116127
return true;
117128
default:
118-
return isTypeDeclInstr(MI) || isConstantInstr(MI) || isDecorationInstr(MI);
129+
return isTypeDeclInstr(MI) || isConstantInstr(MI) ||
130+
isDecorationInstr(MI) || isAliasingInstr(MI);
119131
}
120132
}
121133

‎llvm/lib/Target/SPIRV/SPIRVInstrInfo.h

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@@ -34,6 +34,7 @@ class SPIRVInstrInfo : public SPIRVGenInstrInfo {
3434
bool isInlineAsmDefInstr(const MachineInstr &MI) const;
3535
bool isTypeDeclInstr(const MachineInstr &MI) const;
3636
bool isDecorationInstr(const MachineInstr &MI) const;
37+
bool isAliasingInstr(const MachineInstr &MI) const;
3738
bool canUseFastMathFlags(const MachineInstr &MI) const;
3839
bool canUseNSW(const MachineInstr &MI) const;
3940
bool canUseNUW(const MachineInstr &MI) const;

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