Skip to content

Commit 6e7e46c

Browse files
hchandelsvs-quic
hchandel
and
svs-quic
authored
[RISCV] Add Qualcomm uC Xqcibm (Bit Manipulation) extension (llvm#129504)
This extension adds thirty eight bit manipulation instructions. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.6 This patch adds assembler only support. Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
1 parent b18e5b6 commit 6e7e46c

File tree

15 files changed

+891
-9
lines changed

15 files changed

+891
-9
lines changed

‎clang/test/Driver/print-supported-extensions-riscv.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -196,6 +196,7 @@
196196
// CHECK-NEXT: xqccmp 0.1 'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)
197197
// CHECK-NEXT: xqcia 0.4 'Xqcia' (Qualcomm uC Arithmetic Extension)
198198
// CHECK-NEXT: xqciac 0.3 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)
199+
// CHECK-NEXT: xqcibm 0.4 'Xqcibm' (Qualcomm uC Bit Manipulation Extension)
199200
// CHECK-NEXT: xqcicli 0.2 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)
200201
// CHECK-NEXT: xqcicm 0.2 'Xqcicm' (Qualcomm uC Conditional Move Extension)
201202
// CHECK-NEXT: xqcics 0.2 'Xqcics' (Qualcomm uC Conditional Select Extension)

‎llvm/docs/RISCVUsage.rst

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -438,6 +438,9 @@ The current vendor extensions supported are:
438438
``experimental-Xqciac``
439439
LLVM implements `version 0.3 of the Qualcomm uC Load-Store Address Calculation extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
440440

441+
``experimental-Xqcibm``
442+
LLVM implements `version 0.4 of the Qualcomm uC Bit Manipulation extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
443+
441444
``experimental-Xqcicli``
442445
LLVM implements `version 0.2 of the Qualcomm uC Conditional Load Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
443446

‎llvm/docs/ReleaseNotes.md

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -109,6 +109,8 @@ Changes to the RISC-V Backend
109109

110110
* Adds experimental assembler support for the Qualcomm uC 'Xqcilia` (Large Immediate Arithmetic)
111111
extension.
112+
* Adds experimental assembler support for the Qualcomm uC 'Xqcibm` (Bit Manipulation)
113+
extension.
112114
* Adds experimental assembler and code generation support for the Qualcomm
113115
'Xqccmp' extension, which is a frame-pointer convention compatible version of
114116
Zcmp.

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -745,6 +745,26 @@ struct RISCVOperand final : public MCParsedAsmOperand {
745745
VK == RISCVMCExpr::VK_RISCV_None;
746746
}
747747

748+
bool isUImm5Plus1() const {
749+
if (!isImm())
750+
return false;
751+
RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
752+
int64_t Imm;
753+
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
754+
return IsConstantImm && ((isUInt<5>(Imm) && (Imm != 0)) || (Imm == 32)) &&
755+
VK == RISCVMCExpr::VK_RISCV_None;
756+
}
757+
758+
bool isUImm5GE6Plus1() const {
759+
if (!isImm())
760+
return false;
761+
RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
762+
int64_t Imm;
763+
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
764+
return IsConstantImm && ((isUInt<5>(Imm) && (Imm >= 6)) || (Imm == 32)) &&
765+
VK == RISCVMCExpr::VK_RISCV_None;
766+
}
767+
748768
bool isUImm8GE32() const {
749769
int64_t Imm;
750770
RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
@@ -937,6 +957,16 @@ struct RISCVOperand final : public MCParsedAsmOperand {
937957
return SignExtend64<32>(Imm);
938958
}
939959

960+
bool isSImm11() const {
961+
if (!isImm())
962+
return false;
963+
RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
964+
int64_t Imm;
965+
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
966+
return IsConstantImm && isInt<11>(fixImmediateForRV32(Imm, isRV64Imm())) &&
967+
VK == RISCVMCExpr::VK_RISCV_None;
968+
}
969+
940970
bool isSImm12() const {
941971
RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
942972
int64_t Imm;
@@ -1562,6 +1592,10 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
15621592
return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5) - 1);
15631593
case Match_InvalidUImm5GT3:
15641594
return generateImmOutOfRangeError(Operands, ErrorInfo, 4, (1 << 5) - 1);
1595+
case Match_InvalidUImm5Plus1:
1596+
return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5));
1597+
case Match_InvalidUImm5GE6Plus1:
1598+
return generateImmOutOfRangeError(Operands, ErrorInfo, 6, (1 << 5));
15651599
case Match_InvalidUImm6:
15661600
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 6) - 1);
15671601
case Match_InvalidUImm7:
@@ -1620,6 +1654,9 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
16201654
return generateImmOutOfRangeError(
16211655
Operands, ErrorInfo, -(1 << 9), (1 << 9) - 16,
16221656
"immediate must be a multiple of 16 bytes and non-zero in the range");
1657+
case Match_InvalidSImm11:
1658+
return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 10),
1659+
(1 << 10) - 1);
16231660
case Match_InvalidUImm10:
16241661
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 10) - 1);
16251662
case Match_InvalidUImm11:

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Lines changed: 27 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -341,6 +341,19 @@ static DecodeStatus decodeUImmOperandGE(MCInst &Inst, uint32_t Imm,
341341
return MCDisassembler::Success;
342342
}
343343

344+
template <unsigned Width, unsigned LowerBound>
345+
static DecodeStatus decodeUImmPlus1OperandGE(MCInst &Inst, uint32_t Imm,
346+
int64_t Address,
347+
const MCDisassembler *Decoder) {
348+
assert(isUInt<Width>(Imm) && "Invalid immediate");
349+
350+
if ((Imm + 1) < LowerBound)
351+
return MCDisassembler::Fail;
352+
353+
Inst.addOperand(MCOperand::createImm(Imm + 1));
354+
return MCDisassembler::Success;
355+
}
356+
344357
static DecodeStatus decodeUImmLog2XLenOperand(MCInst &Inst, uint32_t Imm,
345358
int64_t Address,
346359
const MCDisassembler *Decoder) {
@@ -371,6 +384,15 @@ decodeUImmLog2XLenNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address,
371384
return decodeUImmLog2XLenOperand(Inst, Imm, Address, Decoder);
372385
}
373386

387+
template <unsigned N>
388+
static DecodeStatus decodeUImmPlus1Operand(MCInst &Inst, uint32_t Imm,
389+
int64_t Address,
390+
const MCDisassembler *Decoder) {
391+
assert(isUInt<N>(Imm) && "Invalid immediate");
392+
Inst.addOperand(MCOperand::createImm(Imm + 1));
393+
return MCDisassembler::Success;
394+
}
395+
374396
template <unsigned N>
375397
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm,
376398
int64_t Address,
@@ -629,11 +651,11 @@ static constexpr FeatureBitset XRivosFeatureGroup = {
629651

630652
static constexpr FeatureBitset XqciFeatureGroup = {
631653
RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac,
632-
RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm,
633-
RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr,
634-
RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqcilia,
635-
RISCV::FeatureVendorXqcilo, RISCV::FeatureVendorXqcilsm,
636-
RISCV::FeatureVendorXqcisls,
654+
RISCV::FeatureVendorXqcibm, RISCV::FeatureVendorXqcicli,
655+
RISCV::FeatureVendorXqcicm, RISCV::FeatureVendorXqcics,
656+
RISCV::FeatureVendorXqcicsr, RISCV::FeatureVendorXqciint,
657+
RISCV::FeatureVendorXqcilia, RISCV::FeatureVendorXqcilo,
658+
RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisls,
637659
};
638660

639661
static constexpr FeatureBitset XSfVectorGroup = {

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -296,6 +296,8 @@ enum OperandType : unsigned {
296296
OPERAND_UIMM5,
297297
OPERAND_UIMM5_NONZERO,
298298
OPERAND_UIMM5_GT3,
299+
OPERAND_UIMM5_PLUS1,
300+
OPERAND_UIMM5_GE6_PLUS1,
299301
OPERAND_UIMM5_LSB0,
300302
OPERAND_UIMM6,
301303
OPERAND_UIMM6_LSB0,
@@ -324,6 +326,7 @@ enum OperandType : unsigned {
324326
OPERAND_SIMM6,
325327
OPERAND_SIMM6_NONZERO,
326328
OPERAND_SIMM10_LSB0000_NONZERO,
329+
OPERAND_SIMM11,
327330
OPERAND_SIMM12,
328331
OPERAND_SIMM12_LSB00000,
329332
OPERAND_SIMM26,

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -80,6 +80,10 @@ class RISCVMCCodeEmitter : public MCCodeEmitter {
8080
SmallVectorImpl<MCFixup> &Fixups,
8181
const MCSubtargetInfo &STI) const;
8282

83+
uint64_t getImmOpValueMinus1(const MCInst &MI, unsigned OpNo,
84+
SmallVectorImpl<MCFixup> &Fixups,
85+
const MCSubtargetInfo &STI) const;
86+
8387
uint64_t getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
8488
SmallVectorImpl<MCFixup> &Fixups,
8589
const MCSubtargetInfo &STI) const;
@@ -385,6 +389,21 @@ RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
385389
return 0;
386390
}
387391

392+
uint64_t
393+
RISCVMCCodeEmitter::getImmOpValueMinus1(const MCInst &MI, unsigned OpNo,
394+
SmallVectorImpl<MCFixup> &Fixups,
395+
const MCSubtargetInfo &STI) const {
396+
const MCOperand &MO = MI.getOperand(OpNo);
397+
398+
if (MO.isImm()) {
399+
uint64_t Res = MO.getImm();
400+
return (Res - 1);
401+
}
402+
403+
llvm_unreachable("Unhandled expression!");
404+
return 0;
405+
}
406+
388407
uint64_t
389408
RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
390409
SmallVectorImpl<MCFixup> &Fixups,

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1366,6 +1366,14 @@ def HasVendorXqcilia
13661366
AssemblerPredicate<(all_of FeatureVendorXqcilia),
13671367
"'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)">;
13681368

1369+
def FeatureVendorXqcibm
1370+
: RISCVExperimentalExtension<0, 4, "Qualcomm uC Bit Manipulation Extension",
1371+
[FeatureStdExtZca]>;
1372+
def HasVendorXqcibm
1373+
: Predicate<"Subtarget->hasVendorXqcibm()">,
1374+
AssemblerPredicate<(all_of FeatureVendorXqcibm),
1375+
"'Xqcibm' (Qualcomm uC Bit Manipulation Extension)">;
1376+
13691377
def FeatureVendorXqcilo
13701378
: RISCVExperimentalExtension<0, 2, "Qualcomm uC Large Offset Load Store Extension",
13711379
[FeatureStdExtZca]>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

Lines changed: 117 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,10 +28,34 @@ def uimm5gt3 : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
2828
let OperandType = "OPERAND_UIMM5_GT3";
2929
}
3030

31+
def UImm5Plus1AsmOperand : AsmOperandClass {
32+
let Name = "UImm5Plus1";
33+
let RenderMethod = "addImmOperands";
34+
let DiagnosticType = "InvalidUImm5Plus1";
35+
}
36+
37+
def uimm5_plus1 : RISCVOp, ImmLeaf<XLenVT,
38+
[{return (isUInt<5>(Imm) && (Imm != 0)) || (Imm == 32);}]> {
39+
let ParserMatchClass = UImm5Plus1AsmOperand;
40+
let EncoderMethod = "getImmOpValueMinus1";
41+
let DecoderMethod = "decodeUImmPlus1Operand<5>";
42+
let OperandType = "OPERAND_UIMM5_PLUS1";
43+
}
44+
45+
def uimm5ge6_plus1 : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
46+
[{return (Imm >= 6) && (isUInt<5>(Imm) || (Imm == 32));}]> {
47+
let ParserMatchClass = UImmAsmOperand<5, "GE6Plus1">;
48+
let EncoderMethod = "getImmOpValueMinus1";
49+
let DecoderMethod = "decodeUImmPlus1OperandGE<5,6>";
50+
let OperandType = "OPERAND_UIMM5_GE6_PLUS1";
51+
}
52+
3153
def uimm10 : RISCVUImmLeafOp<10>;
3254

3355
def uimm11 : RISCVUImmLeafOp<11>;
3456

57+
def simm11 : RISCVSImmLeafOp<11>;
58+
3559
def simm26 : RISCVSImmLeafOp<26>;
3660

3761
// 32-bit Immediate, used by RV32 Instructions in 32-bit operations, so no
@@ -80,6 +104,11 @@ class QCIStore_ScaleIdx<bits<4> funct4, string opcodestr>
80104
}
81105
}
82106

107+
class QCIRVInstI<bits<4> funct4, string opcodestr>
108+
: RVInstIUnary<{0b000, funct4, 0b00000}, 0b011, OPC_CUSTOM_0,
109+
(outs GPRNoX0:$rd), (ins GPRNoX0:$rs1), opcodestr,
110+
"$rd, $rs1">;
111+
83112
class QCIRVInstR<bits<4> funct4, string opcodestr>
84113
: RVInstR<{0b000, funct4}, 0b011, OPC_CUSTOM_0, (outs GPRNoX0:$rd),
85114
(ins GPRNoX0:$rs1), opcodestr, "$rd, $rs1"> {
@@ -90,6 +119,30 @@ class QCIRVInstRR<bits<5> funct5, DAGOperand InTyRs1, string opcodestr>
90119
: RVInstR<{0b00, funct5}, 0b011, OPC_CUSTOM_0, (outs GPRNoX0:$rd),
91120
(ins InTyRs1:$rs1, GPRNoX0:$rs2), opcodestr, "$rd, $rs1, $rs2">;
92121

122+
class QCIBitManipRII<bits<3> funct3, bits<2> funct2,
123+
DAGOperand InTyRs1, string opcodestr>
124+
: RVInstIBase<funct3, OPC_CUSTOM_0, (outs GPRNoX0:$rd),
125+
(ins InTyRs1:$rs1, uimm5_plus1:$width, uimm5:$shamt),
126+
opcodestr, "$rd, $rs1, $width, $shamt"> {
127+
bits<5> shamt;
128+
bits<5> width;
129+
130+
let Inst{31-30} = funct2;
131+
let Inst{29-25} = width;
132+
let Inst{24-20} = shamt;
133+
}
134+
135+
class QCIRVInstRI<bits<1> funct1, DAGOperand InTyImm11,
136+
string opcodestr>
137+
: RVInstIBase<0b000, OPC_CUSTOM_0, (outs GPRNoX0:$rd),
138+
(ins GPRNoX0:$rs1, InTyImm11:$imm11), opcodestr,
139+
"$rd, $rs1, $imm11"> {
140+
bits<11> imm11;
141+
142+
let Inst{31-31} = funct1;
143+
let Inst{30-20} = imm11;
144+
}
145+
93146
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
94147
class QCISELECTIICC<bits<3> funct3, string opcodestr>
95148
: RVInstR4<0b00, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
@@ -185,6 +238,17 @@ class QCIMVCCI<bits<3> funct3, string opcodestr, DAGOperand immType>
185238
let rs2 = imm;
186239
}
187240

241+
class QCI_RVInst16CB_BM<bits<2> funct2, string opcodestr>
242+
: RVInst16CB<0b100, 0b01, (outs GPRC:$rd),
243+
(ins GPRC:$rs1, uimmlog2xlennonzero:$shamt),
244+
opcodestr, "$rs1, $shamt"> {
245+
bits<5> shamt;
246+
let Constraints = "$rs1 = $rd";
247+
let Inst{12} = 0b1;
248+
let Inst{11-10} = funct2;
249+
let Inst{6-2} = shamt{4-0};
250+
}
251+
188252
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
189253
class QCIRVInst16CI_RS1<bits<5> funct5, string OpcodeStr>
190254
: RVInst16CI<0b000, 0b10, (outs), (ins GPRNoX0:$rs1), OpcodeStr, "$rs1"> {
@@ -333,6 +397,59 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
333397
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
334398
} // Predicates = [HasVendorXqcia, IsRV32]
335399

400+
let Predicates = [HasVendorXqcibm, IsRV32] in {
401+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
402+
def QC_INSBRI : QCIRVInstRI<0b1, simm11, "qc.insbri">;
403+
def QC_INSBI : RVInstIBase<0b001, OPC_CUSTOM_0, (outs GPRNoX0:$rd),
404+
(ins simm5:$imm5, uimm5_plus1:$width,
405+
uimm5:$shamt), "qc.insbi",
406+
"$rd, $imm5, $width, $shamt"> {
407+
bits<5> imm5;
408+
bits<5> shamt;
409+
bits<5> width;
410+
let rs1 = imm5;
411+
let Inst{31-30} = 0b00;
412+
let Inst{29-25} = width;
413+
let Inst{24-20} = shamt;
414+
}
415+
def QC_INSB : QCIBitManipRII<0b001, 0b01, GPR, "qc.insb">;
416+
def QC_INSBH : QCIBitManipRII<0b001, 0b10, GPR, "qc.insbh">;
417+
def QC_INSBR : QCIRVInstRR<0b00000, GPR, "qc.insbr">;
418+
def QC_INSBHR : QCIRVInstRR<0b00001, GPR, "qc.insbhr">;
419+
def QC_INSBPR : QCIRVInstRR<0b00010, GPR, "qc.insbpr">;
420+
def QC_INSBPRH : QCIRVInstRR<0b00011, GPR, "qc.insbprh">;
421+
def QC_EXTU : QCIBitManipRII<0b010, 0b00, GPRNoX0, "qc.extu">;
422+
def QC_EXTDU : QCIBitManipRII<0b010, 0b10, GPR, "qc.extdu">;
423+
def QC_EXTDUR : QCIRVInstRR<0b00100, GPR, "qc.extdur">;
424+
def QC_EXTDUPR : QCIRVInstRR<0b00110, GPR, "qc.extdupr">;
425+
def QC_EXTDUPRH : QCIRVInstRR<0b00111, GPR, "qc.extduprh">;
426+
def QC_EXT : QCIBitManipRII<0b010, 0b01, GPRNoX0, "qc.ext">;
427+
def QC_EXTD : QCIBitManipRII<0b010, 0b11, GPR, "qc.extd">;
428+
def QC_EXTDR : QCIRVInstRR<0b00101, GPR, "qc.extdr">;
429+
def QC_EXTDPR : QCIRVInstRR<0b01000, GPR, "qc.extdpr">;
430+
def QC_EXTDPRH : QCIRVInstRR<0b01001, GPR, "qc.extdprh">;
431+
def QC_COMPRESS2 : QCIRVInstI<0b0000, "qc.compress2">;
432+
def QC_COMPRESS3 : QCIRVInstI<0b0001, "qc.compress3">;
433+
def QC_EXPAND2 : QCIRVInstI<0b0010, "qc.expand2">;
434+
def QC_EXPAND3 : QCIRVInstI<0b0011, "qc.expand3">;
435+
def QC_CLO : QCIRVInstI<0b0100, "qc.clo">;
436+
def QC_CTO : QCIRVInstI<0b0101, "qc.cto">;
437+
def QC_BREV32 : QCIRVInstI<0b0110, "qc.brev32">;
438+
def QC_C_BEXTI : QCI_RVInst16CB_BM<0b00, "qc.c.bexti">;
439+
def QC_C_BSETI : QCI_RVInst16CB_BM<0b01, "qc.c.bseti">;
440+
def QC_C_EXTU : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd_wb),
441+
(ins GPRNoX0:$rd, uimm5ge6_plus1:$width),
442+
"qc.c.extu", "$rd, $width"> {
443+
bits<5> rd;
444+
bits<5> width;
445+
let Constraints = "$rd = $rd_wb";
446+
let Inst{6-2} = width;
447+
let Inst{11-7} = rd;
448+
let Inst{12} = 0b1;
449+
}
450+
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
451+
} // Predicates = [HasVendorXqcibm, IsRV32]
452+
336453
let Predicates = [HasVendorXqciac, IsRV32] in {
337454
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
338455
def QC_C_MULIADD : RVInst16CL<0b001, 0b10, (outs GPRC:$rd_wb),

‎llvm/lib/TargetParser/RISCVISAInfo.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -742,9 +742,9 @@ Error RISCVISAInfo::checkDependency() {
742742
bool HasZvl = MinVLen != 0;
743743
bool HasZcmt = Exts.count("zcmt") != 0;
744744
static constexpr StringLiteral XqciExts[] = {
745-
{"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcicm"},
746-
{"xqcics"}, {"xqcicsr"}, {"xqciint"}, {"xqcilia"},
747-
{"xqcilo"}, {"xqcilsm"}, {"xqcisls"}};
745+
{"xqcia"}, {"xqciac"}, {"xqcibm"}, {"xqcicli"},
746+
{"xqcicm"}, {"xqcics"}, {"xqcicsr"}, {"xqciint"},
747+
{"xqcilia"}, {"xqcilo"}, {"xqcilsm"}, {"xqcisls"}};
748748
bool HasZcmp = Exts.count("zcmp") != 0;
749749
bool HasXqccmp = Exts.count("xqccmp") != 0;
750750

0 commit comments

Comments
 (0)