@@ -15,31 +15,31 @@ RasterizerOrderedStructuredBuffer<float> Buf5 : register(u1, space2);
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// CHECK: %"class.hlsl::ConsumeStructuredBuffer" = type { target("dx.RawBuffer", float, 1, 0) }
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// CHECK: %"class.hlsl::RasterizerOrderedStructuredBuffer" = type { target("dx.RawBuffer", float, 1, 1) }
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- // CHECK: @Buf = global %"class.hlsl::StructuredBuffer" zeroinitializer , align 4
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- // CHECK: @Buf2 = global %"class.hlsl::RWStructuredBuffer" zeroinitializer , align 4
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- // CHECK: @Buf3 = global %"class.hlsl::AppendStructuredBuffer" zeroinitializer , align 4
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- // CHECK: @Buf4 = global %"class.hlsl::ConsumeStructuredBuffer" zeroinitializer , align 4
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- // CHECK: @Buf5 = global %"class.hlsl::RasterizerOrderedStructuredBuffer" zeroinitializer , align 4
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+ // CHECK: @_ZL3Buf = internal global %"class.hlsl::StructuredBuffer" poison , align 4
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+ // CHECK: @_ZL4Buf2 = internal global %"class.hlsl::RWStructuredBuffer" poison , align 4
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+ // CHECK: @_ZL4Buf3 = internal global %"class.hlsl::AppendStructuredBuffer" poison , align 4
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+ // CHECK: @_ZL4Buf4 = internal global %"class.hlsl::ConsumeStructuredBuffer" poison , align 4
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+ // CHECK: @_ZL4Buf5 = internal global %"class.hlsl::RasterizerOrderedStructuredBuffer" poison , align 4
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- // CHECK: define internal void @_init_resource_Buf ()
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- // CHECK-DXIL: %Buf_h = call target("dx.RawBuffer", float, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_0_0t(i32 0, i32 10, i32 1, i32 0, i1 false)
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- // CHECK-DXIL: store target("dx.RawBuffer", float, 0, 0) %Buf_h , ptr @Buf , align 4
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+ // CHECK: define internal void @_init_resource__ZL3Buf ()
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+ // CHECK-DXIL: [[H:%.*]] = call target("dx.RawBuffer", float, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_0_0t(i32 0, i32 10, i32 1, i32 0, i1 false)
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+ // CHECK-DXIL: store target("dx.RawBuffer", float, 0, 0) [[H]] , ptr @_ZL3Buf , align 4
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- // CHECK: define internal void @_init_resource_Buf2 ()
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- // CHECK-DXIL: %Buf2_h = call target("dx.RawBuffer", float, 1, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_1_0t(i32 1, i32 5, i32 1, i32 0, i1 false)
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- // CHECK-DXIL: store target("dx.RawBuffer", float, 1, 0) %Buf2_h , ptr @Buf2 , align 4
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+ // CHECK: define internal void @_init_resource__ZL4Buf2 ()
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+ // CHECK-DXIL: [[H:%.*]] = call target("dx.RawBuffer", float, 1, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_1_0t(i32 1, i32 5, i32 1, i32 0, i1 false)
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+ // CHECK-DXIL: store target("dx.RawBuffer", float, 1, 0) [[H]] , ptr @_ZL4Buf2 , align 4
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- // CHECK: define internal void @_init_resource_Buf3 ()
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- // CHECK-DXIL: %Buf3_h = call target("dx.RawBuffer", float, 1, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_1_0t(i32 0, i32 3, i32 1, i32 0, i1 false)
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- // CHECK-DXIL: store target("dx.RawBuffer", float, 1, 0) %Buf3_h , ptr @Buf3 , align 4
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+ // CHECK: define internal void @_init_resource__ZL4Buf3 ()
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+ // CHECK-DXIL: [[H:%.*]] = call target("dx.RawBuffer", float, 1, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_1_0t(i32 0, i32 3, i32 1, i32 0, i1 false)
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+ // CHECK-DXIL: store target("dx.RawBuffer", float, 1, 0) [[H]] , ptr @_ZL4Buf3 , align 4
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- // CHECK: define internal void @_init_resource_Buf4 ()
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- // CHECK-DXIL: %Buf4_h = call target("dx.RawBuffer", float, 1, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_1_0t(i32 0, i32 4, i32 1, i32 0, i1 false)
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- // CHECK-DXIL: store target("dx.RawBuffer", float, 1, 0) %Buf4_h , ptr @Buf4 , align 4
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+ // CHECK: define internal void @_init_resource__ZL4Buf4 ()
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+ // CHECK-DXIL: [[H:%.*]] = call target("dx.RawBuffer", float, 1, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_1_0t(i32 0, i32 4, i32 1, i32 0, i1 false)
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+ // CHECK-DXIL: store target("dx.RawBuffer", float, 1, 0) [[H]] , ptr @_ZL4Buf4 , align 4
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- // CHECK: define internal void @_init_resource_Buf5 ()
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- // CHECK-DXIL: %Buf5_h = call target("dx.RawBuffer", float, 1, 1) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_1_1t(i32 2, i32 1, i32 1, i32 0, i1 false)
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- // CHECK-DXIL: store target("dx.RawBuffer", float, 1, 1) %Buf5_h , ptr @Buf5 , align 4
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+ // CHECK: define internal void @_init_resource__ZL4Buf5 ()
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+ // CHECK-DXIL: [[H:%.*]] = call target("dx.RawBuffer", float, 1, 1) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_1_1t(i32 2, i32 1, i32 1, i32 0, i1 false)
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+ // CHECK-DXIL: store target("dx.RawBuffer", float, 1, 1) [[H]] , ptr @_ZL4Buf5 , align 4
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// CHECK: define linkonce_odr void @_ZN4hlsl16StructuredBufferIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) %this)
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// CHECK-NEXT: entry:
@@ -52,8 +52,8 @@ RasterizerOrderedStructuredBuffer<float> Buf5 : register(u1, space2);
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// CHECK-NEXT: entry:
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// CHECK: define internal void @_GLOBAL__sub_I_StructuredBuffers_constructors.hlsl()
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- // CHECK: call void @_init_resource_Buf ()
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- // CHECK: call void @_init_resource_Buf2 ()
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- // CHECK: call void @_init_resource_Buf3 ()
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- // CHECK: call void @_init_resource_Buf4 ()
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- // CHECK: call void @_init_resource_Buf5 ()
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+ // CHECK: call void @_init_resource__ZL3Buf ()
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+ // CHECK: call void @_init_resource__ZL4Buf2 ()
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+ // CHECK: call void @_init_resource__ZL4Buf3 ()
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+ // CHECK: call void @_init_resource__ZL4Buf4 ()
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+ // CHECK: call void @_init_resource__ZL4Buf5 ()
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