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‎clang/docs/LanguageExtensions.rst

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1803,10 +1803,6 @@ The following type trait primitives are supported by Clang. Those traits marked
18031803
* ``__is_pointer_interconvertible_base_of`` (C++, GNU, Microsoft)
18041804
* ``__is_polymorphic`` (C++, GNU, Microsoft, Embarcadero)
18051805
* ``__is_reference`` (C++, Embarcadero)
1806-
* ``__is_referenceable`` (C++, GNU, Microsoft, Embarcadero):
1807-
Returns true if a type is referenceable, and false otherwise. A referenceable
1808-
type is a type that's either an object type, a reference type, or an unqualified
1809-
function type. This trait is deprecated and will be removed in Clang 21.
18101806
* ``__is_rvalue_reference`` (C++, Embarcadero)
18111807
* ``__is_same`` (C++, Embarcadero)
18121808
* ``__is_same_as`` (GCC): Synonym for ``__is_same``.

‎clang/docs/ReleaseNotes.rst

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,10 @@ C/C++ Language Potentially Breaking Changes
4242
C++ Specific Potentially Breaking Changes
4343
-----------------------------------------
4444

45+
- The type trait builtin ``__is_referenceable`` has been removed, since it has
46+
very few users and all the type traits that could benefit from it in the
47+
standard library already have their own bespoke builtins.
48+
4549
ABI Changes in This Version
4650
---------------------------
4751

‎clang/include/clang/Basic/TokenKinds.def

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -546,7 +546,6 @@ TYPE_TRAIT_1(__is_trivially_equality_comparable, IsTriviallyEqualityComparable,
546546
TYPE_TRAIT_1(__is_bounded_array, IsBoundedArray, KEYCXX)
547547
TYPE_TRAIT_1(__is_unbounded_array, IsUnboundedArray, KEYCXX)
548548
TYPE_TRAIT_1(__is_scoped_enum, IsScopedEnum, KEYCXX)
549-
TYPE_TRAIT_1(__is_referenceable, IsReferenceable, KEYCXX)
550549
TYPE_TRAIT_1(__can_pass_in_regs, CanPassInRegs, KEYCXX)
551550
TYPE_TRAIT_2(__reference_binds_to_temporary, ReferenceBindsToTemporary, KEYCXX)
552551
TYPE_TRAIT_2(__reference_constructs_from_temporary, ReferenceConstructsFromTemporary, KEYCXX)

‎clang/include/clang/Basic/arm_sme.td

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -110,11 +110,11 @@ multiclass ZARead<string n_suffix, string t, string i_prefix, list<ImmCheck> ch>
110110
}
111111
}
112112

113-
defm SVREAD_ZA8 : ZARead<"za8", "cUc", "aarch64_sme_read", [ImmCheck<2, ImmCheck0_0>]>;
113+
defm SVREAD_ZA8 : ZARead<"za8", "cUcm", "aarch64_sme_read", [ImmCheck<2, ImmCheck0_0>]>;
114114
defm SVREAD_ZA16 : ZARead<"za16", "sUshb", "aarch64_sme_read", [ImmCheck<2, ImmCheck0_1>]>;
115115
defm SVREAD_ZA32 : ZARead<"za32", "iUif", "aarch64_sme_read", [ImmCheck<2, ImmCheck0_3>]>;
116116
defm SVREAD_ZA64 : ZARead<"za64", "lUld", "aarch64_sme_read", [ImmCheck<2, ImmCheck0_7>]>;
117-
defm SVREAD_ZA128 : ZARead<"za128", "csilUcUsUiUlhbfd", "aarch64_sme_readq", [ImmCheck<2, ImmCheck0_15>]>;
117+
defm SVREAD_ZA128 : ZARead<"za128", "csilUcUsUiUlmhbfd", "aarch64_sme_readq", [ImmCheck<2, ImmCheck0_15>]>;
118118

119119
////////////////////////////////////////////////////////////////////////////////
120120
// Write horizontal/vertical ZA slices
@@ -131,11 +131,11 @@ multiclass ZAWrite<string n_suffix, string t, string i_prefix, list<ImmCheck> ch
131131
}
132132
}
133133

134-
defm SVWRITE_ZA8 : ZAWrite<"za8", "cUc", "aarch64_sme_write", [ImmCheck<0, ImmCheck0_0>]>;
134+
defm SVWRITE_ZA8 : ZAWrite<"za8", "cUcm", "aarch64_sme_write", [ImmCheck<0, ImmCheck0_0>]>;
135135
defm SVWRITE_ZA16 : ZAWrite<"za16", "sUshb", "aarch64_sme_write", [ImmCheck<0, ImmCheck0_1>]>;
136136
defm SVWRITE_ZA32 : ZAWrite<"za32", "iUif", "aarch64_sme_write", [ImmCheck<0, ImmCheck0_3>]>;
137137
defm SVWRITE_ZA64 : ZAWrite<"za64", "lUld", "aarch64_sme_write", [ImmCheck<0, ImmCheck0_7>]>;
138-
defm SVWRITE_ZA128 : ZAWrite<"za128", "csilUcUsUiUlhbfd", "aarch64_sme_writeq", [ImmCheck<0, ImmCheck0_15>]>;
138+
defm SVWRITE_ZA128 : ZAWrite<"za128", "csilUcUsUiUlmhbfd", "aarch64_sme_writeq", [ImmCheck<0, ImmCheck0_15>]>;
139139

140140
////////////////////////////////////////////////////////////////////////////////
141141
// SME - Zero
@@ -350,7 +350,7 @@ multiclass ZAWrite_VG<string n, string t, string i, list<ImmCheck> checks> {
350350
}
351351

352352
let SMETargetGuard = "sme2" in {
353-
defm SVWRITE_ZA8 : ZAWrite_VG<"za8", "cUc", "aarch64_sme_write", [ImmCheck<0, ImmCheck0_0>]>;
353+
defm SVWRITE_ZA8 : ZAWrite_VG<"za8", "cUcm", "aarch64_sme_write", [ImmCheck<0, ImmCheck0_0>]>;
354354
defm SVWRITE_ZA16 : ZAWrite_VG<"za16", "sUshb", "aarch64_sme_write", [ImmCheck<0, ImmCheck0_1>]>;
355355
defm SVWRITE_ZA32 : ZAWrite_VG<"za32", "iUif", "aarch64_sme_write", [ImmCheck<0, ImmCheck0_3>]>;
356356
defm SVWRITE_ZA64 : ZAWrite_VG<"za64", "lUld", "aarch64_sme_write", [ImmCheck<0, ImmCheck0_7>]>;
@@ -366,7 +366,7 @@ multiclass ZARead_VG<string n, string t, string i, list<ImmCheck> checks> {
366366
}
367367

368368
let SMETargetGuard = "sme2" in {
369-
defm SVREAD_ZA8 : ZARead_VG<"za8", "cUc", "aarch64_sme_read", [ImmCheck<0, ImmCheck0_0>]>;
369+
defm SVREAD_ZA8 : ZARead_VG<"za8", "cUcm", "aarch64_sme_read", [ImmCheck<0, ImmCheck0_0>]>;
370370
defm SVREAD_ZA16 : ZARead_VG<"za16", "sUshb", "aarch64_sme_read", [ImmCheck<0, ImmCheck0_1>]>;
371371
defm SVREAD_ZA32 : ZARead_VG<"za32", "iUif", "aarch64_sme_read", [ImmCheck<0, ImmCheck0_3>]>;
372372
defm SVREAD_ZA64 : ZARead_VG<"za64", "lUld", "aarch64_sme_read", [ImmCheck<0, ImmCheck0_7>]>;
@@ -722,24 +722,24 @@ def IN_STREAMING_MODE : Inst<"__arm_in_streaming_mode", "sv", "Pc", MergeNone,
722722
// lookup table expand four contiguous registers
723723
//
724724
let SMETargetGuard = "sme2" in {
725-
def SVLUTI2_LANE_ZT_X4 : Inst<"svluti2_lane_zt_{d}_x4", "4.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x4", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
725+
def SVLUTI2_LANE_ZT_X4 : Inst<"svluti2_lane_zt_{d}_x4", "4.di[i", "cUcsUsiUimbhf", MergeNone, "aarch64_sme_luti2_lane_zt_x4", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
726726
def SVLUTI4_LANE_ZT_X4 : Inst<"svluti4_lane_zt_{d}_x4", "4.di[i", "sUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x4", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_1>]>;
727727
}
728728

729729
//
730730
// lookup table expand one register
731731
//
732732
let SMETargetGuard = "sme2" in {
733-
def SVLUTI2_LANE_ZT : Inst<"svluti2_lane_zt_{d}", "di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_15>]>;
734-
def SVLUTI4_LANE_ZT : Inst<"svluti4_lane_zt_{d}", "di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
733+
def SVLUTI2_LANE_ZT : Inst<"svluti2_lane_zt_{d}", "di[i", "cUcsUsiUimbhf", MergeNone, "aarch64_sme_luti2_lane_zt", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_15>]>;
734+
def SVLUTI4_LANE_ZT : Inst<"svluti4_lane_zt_{d}", "di[i", "cUcsUsiUimbhf", MergeNone, "aarch64_sme_luti4_lane_zt", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
735735
}
736736

737737
//
738738
// lookup table expand two contiguous registers
739739
//
740740
let SMETargetGuard = "sme2" in {
741-
def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
742-
def SVLUTI4_LANE_ZT_X2 : Inst<"svluti4_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x2", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
741+
def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUimbhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
742+
def SVLUTI4_LANE_ZT_X2 : Inst<"svluti4_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUimbhf", MergeNone, "aarch64_sme_luti4_lane_zt_x2", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
743743
}
744744

745745
//
@@ -811,12 +811,12 @@ multiclass ZAReadz<string n_suffix, string vg_num, string t, string i_prefix, li
811811
}
812812
}
813813

814-
defm SVREADZ_ZA8_X2 : ZAReadz<"za8", "2", "cUc", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_0>]>;
814+
defm SVREADZ_ZA8_X2 : ZAReadz<"za8", "2", "cUcm", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_0>]>;
815815
defm SVREADZ_ZA16_X2 : ZAReadz<"za16", "2", "sUshb", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_1>]>;
816816
defm SVREADZ_ZA32_X2 : ZAReadz<"za32", "2", "iUif", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_3>]>;
817817
defm SVREADZ_ZA64_X2 : ZAReadz<"za64", "2", "lUld", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_7>]>;
818818

819-
defm SVREADZ_ZA8_X4 : ZAReadz<"za8", "4", "cUc", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_0>]>;
819+
defm SVREADZ_ZA8_X4 : ZAReadz<"za8", "4", "cUcm", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_0>]>;
820820
defm SVREADZ_ZA16_X4 : ZAReadz<"za16", "4", "sUshb", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_1>]>;
821821
defm SVREADZ_ZA32_X4 : ZAReadz<"za32", "4", "iUif", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_3>]>;
822822
defm SVREADZ_ZA64_X4 : ZAReadz<"za64", "4", "lUld", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_7>]>;
@@ -834,15 +834,15 @@ multiclass ZAReadzSingle<string n_suffix, string t, string i_prefix, list<ImmChe
834834
}
835835
}
836836

837-
defm SVREADZ_ZA8 : ZAReadzSingle<"za8", "cUc", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_0>]>;
837+
defm SVREADZ_ZA8 : ZAReadzSingle<"za8", "cUcm", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_0>]>;
838838
defm SVREADZ_ZA16 : ZAReadzSingle<"za16", "sUshb", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_1>]>;
839839
defm SVREADZ_ZA32 : ZAReadzSingle<"za32", "iUif", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_3>]>;
840840
defm SVREADZ_ZA64 : ZAReadzSingle<"za64", "lUld", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_7>]>;
841-
defm SVREADZ_ZA128 : ZAReadzSingle<"za128", "csilUcUiUsUlbhfd", "aarch64_sme_readz_q", [ImmCheck<0, ImmCheck0_15>]>;
841+
defm SVREADZ_ZA128 : ZAReadzSingle<"za128", "csilUcUiUsUlmbhfd", "aarch64_sme_readz_q", [ImmCheck<0, ImmCheck0_15>]>;
842842

843843
multiclass ZAReadzArray<string vg_num>{
844844
let SMETargetGuard = "sme2p1" in {
845-
def NAME # _B : SInst<"svreadz_za8_{d}_vg1x" # vg_num, vg_num # "m", "cUc", MergeNone, "aarch64_sme_readz_x" # vg_num, [IsStreaming, IsInOutZA]>;
845+
def NAME # _B : SInst<"svreadz_za8_{d}_vg1x" # vg_num, vg_num # "m", "cUcm", MergeNone, "aarch64_sme_readz_x" # vg_num, [IsStreaming, IsInOutZA]>;
846846
def NAME # _H : SInst<"svreadz_za16_{d}_vg1x" # vg_num, vg_num # "m", "sUsbh", MergeNone, "aarch64_sme_readz_x" # vg_num, [IsStreaming, IsInOutZA]>;
847847
def NAME # _S : SInst<"svreadz_za32_{d}_vg1x" # vg_num, vg_num # "m", "iUif", MergeNone, "aarch64_sme_readz_x" # vg_num, [IsStreaming, IsInOutZA]>;
848848
def NAME # _D : SInst<"svreadz_za64_{d}_vg1x" # vg_num, vg_num # "m", "lUld", MergeNone, "aarch64_sme_readz_x" # vg_num, [IsStreaming, IsInOutZA]>;

‎clang/include/clang/Basic/arm_sve.td

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -2104,7 +2104,7 @@ let SVETargetGuard = "sve2p1", SMETargetGuard = "sme" in {
21042104
def SVSCLAMP : SInst<"svclamp[_{d}]", "dddd", "csil", MergeNone, "aarch64_sve_sclamp", [VerifyRuntimeMode], []>;
21052105
def SVUCLAMP : SInst<"svclamp[_{d}]", "dddd", "UcUsUiUl", MergeNone, "aarch64_sve_uclamp", [VerifyRuntimeMode], []>;
21062106

2107-
defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUlbhfd", "aarch64_sve_revd">;
2107+
defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUlmbhfd", "aarch64_sve_revd">;
21082108
}
21092109

21102110
let SVETargetGuard = "sve2p1", SMETargetGuard = "sme2" in {
@@ -2223,8 +2223,8 @@ let SVETargetGuard = InvalidMode, SMETargetGuard = "sme2" in {
22232223
def SVADD_SINGLE_X4 : SInst<"svadd[_single_{d}_x4]", "44d", "cUcsUsiUilUl", MergeNone, "aarch64_sve_add_single_x4", [IsStreaming], []>;
22242224

22252225
// 2-way and 4-way selects
2226-
def SVSEL_X2 : SInst<"svsel[_{d}_x2]", "2}22", "cUcsUsiUilUlbhfd", MergeNone, "aarch64_sve_sel_x2", [IsStreaming], []>;
2227-
def SVSEL_X4 : SInst<"svsel[_{d}_x4]", "4}44", "cUcsUsiUilUlbhfd", MergeNone, "aarch64_sve_sel_x4", [IsStreaming], []>;
2226+
def SVSEL_X2 : SInst<"svsel[_{d}_x2]", "2}22", "cUcsUsiUilUlmbhfd", MergeNone, "aarch64_sve_sel_x2", [IsStreaming], []>;
2227+
def SVSEL_X4 : SInst<"svsel[_{d}_x4]", "4}44", "cUcsUsiUilUlmbhfd", MergeNone, "aarch64_sve_sel_x4", [IsStreaming], []>;
22282228

22292229
// SRSHL / URSHL
22302230
def SVSRSHL_SINGLE_X2 : SInst<"svrshl[_single_{d}_x2]", "22d", "csil", MergeNone, "aarch64_sve_srshl_single_x2", [IsStreaming], []>;
@@ -2402,15 +2402,15 @@ let SVETargetGuard = InvalidMode, SMETargetGuard = "sme2" in {
24022402
//
24032403

24042404
let SVETargetGuard = InvalidMode, SMETargetGuard = "sme2" in {
2405-
def SVZIP_X2 : SInst<"svzip[_{d}_x2]", "22", "cUcsUsiUilUlbhfd", MergeNone, "aarch64_sve_zip_x2", [IsStreaming], []>;
2406-
def SVZIPQ_X2 : SInst<"svzipq[_{d}_x2]", "22", "cUcsUsiUilUlbhfd", MergeNone, "aarch64_sve_zipq_x2", [IsStreaming], []>;
2407-
def SVZIP_X4 : SInst<"svzip[_{d}_x4]", "44", "cUcsUsiUilUlbhfd", MergeNone, "aarch64_sve_zip_x4", [IsStreaming], []>;
2408-
def SVZIPQ_X4 : SInst<"svzipq[_{d}_x4]", "44", "cUcsUsiUilUlbhfd", MergeNone, "aarch64_sve_zipq_x4", [IsStreaming], []>;
2409-
2410-
def SVUZP_X2 : SInst<"svuzp[_{d}_x2]", "22", "cUcsUsiUilUlbhfd", MergeNone, "aarch64_sve_uzp_x2", [IsStreaming], []>;
2411-
def SVUZPQ_X2 : SInst<"svuzpq[_{d}_x2]", "22", "cUcsUsiUilUlbhfd", MergeNone, "aarch64_sve_uzpq_x2", [IsStreaming], []>;
2412-
def SVUZP_X4 : SInst<"svuzp[_{d}_x4]", "44", "cUcsUsiUilUlbhfd", MergeNone, "aarch64_sve_uzp_x4", [IsStreaming], []>;
2413-
def SVUZPQ_X4 : SInst<"svuzpq[_{d}_x4]", "44", "cUcsUsiUilUlbhfd", MergeNone, "aarch64_sve_uzpq_x4", [IsStreaming], []>;
2405+
def SVZIP_X2 : SInst<"svzip[_{d}_x2]", "22", "cUcsUsiUilUlmbhfd", MergeNone, "aarch64_sve_zip_x2", [IsStreaming], []>;
2406+
def SVZIPQ_X2 : SInst<"svzipq[_{d}_x2]", "22", "cUcsUsiUilUlmbhfd", MergeNone, "aarch64_sve_zipq_x2", [IsStreaming], []>;
2407+
def SVZIP_X4 : SInst<"svzip[_{d}_x4]", "44", "cUcsUsiUilUlmbhfd", MergeNone, "aarch64_sve_zip_x4", [IsStreaming], []>;
2408+
def SVZIPQ_X4 : SInst<"svzipq[_{d}_x4]", "44", "cUcsUsiUilUlmbhfd", MergeNone, "aarch64_sve_zipq_x4", [IsStreaming], []>;
2409+
2410+
def SVUZP_X2 : SInst<"svuzp[_{d}_x2]", "22", "cUcsUsiUilUlmbhfd", MergeNone, "aarch64_sve_uzp_x2", [IsStreaming], []>;
2411+
def SVUZPQ_X2 : SInst<"svuzpq[_{d}_x2]", "22", "cUcsUsiUilUlmbhfd", MergeNone, "aarch64_sve_uzpq_x2", [IsStreaming], []>;
2412+
def SVUZP_X4 : SInst<"svuzp[_{d}_x4]", "44", "cUcsUsiUilUlmbhfd", MergeNone, "aarch64_sve_uzp_x4", [IsStreaming], []>;
2413+
def SVUZPQ_X4 : SInst<"svuzpq[_{d}_x4]", "44", "cUcsUsiUilUlmbhfd", MergeNone, "aarch64_sve_uzpq_x4", [IsStreaming], []>;
24142414
}
24152415

24162416
//

‎clang/lib/CodeGen/CGCUDANV.cpp

Lines changed: 12 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -40,8 +40,6 @@ class CGNVCUDARuntime : public CGCUDARuntime {
4040

4141
/// The prefix used for function calls and section names (CUDA, HIP, LLVM)
4242
StringRef Prefix;
43-
/// TODO: We should transition the OpenMP section to LLVM/Offload
44-
StringRef SectionPrefix;
4543

4644
private:
4745
llvm::IntegerType *IntTy, *SizeTy;
@@ -234,13 +232,12 @@ CGNVCUDARuntime::CGNVCUDARuntime(CodeGenModule &CGM)
234232
VoidTy = CGM.VoidTy;
235233
PtrTy = CGM.UnqualPtrTy;
236234

237-
if (CGM.getLangOpts().OffloadViaLLVM) {
235+
if (CGM.getLangOpts().OffloadViaLLVM)
238236
Prefix = "llvm";
239-
SectionPrefix = "omp";
240-
} else if (CGM.getLangOpts().HIP)
241-
SectionPrefix = Prefix = "hip";
237+
else if (CGM.getLangOpts().HIP)
238+
Prefix = "hip";
242239
else
243-
SectionPrefix = Prefix = "cuda";
240+
Prefix = "cuda";
244241
}
245242

246243
llvm::FunctionCallee CGNVCUDARuntime::getSetupArgumentFn() const {
@@ -1198,17 +1195,19 @@ void CGNVCUDARuntime::transformManagedVars() {
11981195
// register the symbols with the linked device image.
11991196
void CGNVCUDARuntime::createOffloadingEntries() {
12001197
SmallVector<char, 32> Out;
1201-
StringRef Section = (SectionPrefix + "_offloading_entries").toStringRef(Out);
12021198
llvm::object::OffloadKind Kind = CGM.getLangOpts().HIP
12031199
? llvm::object::OffloadKind::OFK_HIP
12041200
: llvm::object::OffloadKind::OFK_Cuda;
1201+
// For now, just spoof this as OpenMP because that's the runtime it uses.
1202+
if (CGM.getLangOpts().OffloadViaLLVM)
1203+
Kind = llvm::object::OffloadKind::OFK_OpenMP;
12051204

12061205
llvm::Module &M = CGM.getModule();
12071206
for (KernelInfo &I : EmittedKernels)
12081207
llvm::offloading::emitOffloadingEntry(
12091208
M, Kind, KernelHandles[I.Kernel->getName()],
12101209
getDeviceSideName(cast<NamedDecl>(I.D)), /*Flags=*/0, /*Data=*/0,
1211-
llvm::offloading::OffloadGlobalEntry, Section);
1210+
llvm::offloading::OffloadGlobalEntry);
12121211

12131212
for (VarInfo &I : DeviceVars) {
12141213
uint64_t VarSize =
@@ -1233,23 +1232,23 @@ void CGNVCUDARuntime::createOffloadingEntries() {
12331232
llvm::offloading::emitOffloadingEntry(
12341233
M, Kind, I.Var, getDeviceSideName(I.D), VarSize,
12351234
llvm::offloading::OffloadGlobalManagedEntry | Flags,
1236-
/*Data=*/I.Var->getAlignment(), Section, ManagedVar);
1235+
/*Data=*/I.Var->getAlignment(), ManagedVar);
12371236
} else {
12381237
llvm::offloading::emitOffloadingEntry(
12391238
M, Kind, I.Var, getDeviceSideName(I.D), VarSize,
12401239
llvm::offloading::OffloadGlobalEntry | Flags,
1241-
/*Data=*/0, Section);
1240+
/*Data=*/0);
12421241
}
12431242
} else if (I.Flags.getKind() == DeviceVarFlags::Surface) {
12441243
llvm::offloading::emitOffloadingEntry(
12451244
M, Kind, I.Var, getDeviceSideName(I.D), VarSize,
12461245
llvm::offloading::OffloadGlobalSurfaceEntry | Flags,
1247-
I.Flags.getSurfTexType(), Section);
1246+
I.Flags.getSurfTexType());
12481247
} else if (I.Flags.getKind() == DeviceVarFlags::Texture) {
12491248
llvm::offloading::emitOffloadingEntry(
12501249
M, Kind, I.Var, getDeviceSideName(I.D), VarSize,
12511250
llvm::offloading::OffloadGlobalTextureEntry | Flags,
1252-
I.Flags.getSurfTexType(), Section);
1251+
I.Flags.getSurfTexType());
12531252
}
12541253
}
12551254
}

‎clang/lib/Parse/ParseDeclCXX.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1813,7 +1813,6 @@ void Parser::ParseClassSpecifier(tok::TokenKind TagTokKind,
18131813
tok::kw___is_pointer,
18141814
tok::kw___is_polymorphic,
18151815
tok::kw___is_reference,
1816-
tok::kw___is_referenceable,
18171816
tok::kw___is_rvalue_expr,
18181817
tok::kw___is_rvalue_reference,
18191818
tok::kw___is_same,

‎clang/lib/Parse/ParseExpr.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -824,7 +824,6 @@ bool Parser::isRevertibleTypeTrait(const IdentifierInfo *II,
824824
REVERTIBLE_TYPE_TRAIT(__is_pointer);
825825
REVERTIBLE_TYPE_TRAIT(__is_polymorphic);
826826
REVERTIBLE_TYPE_TRAIT(__is_reference);
827-
REVERTIBLE_TYPE_TRAIT(__is_referenceable);
828827
REVERTIBLE_TYPE_TRAIT(__is_rvalue_expr);
829828
REVERTIBLE_TYPE_TRAIT(__is_rvalue_reference);
830829
REVERTIBLE_TYPE_TRAIT(__is_same);

‎clang/lib/Sema/SemaExprCXX.cpp

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5032,7 +5032,6 @@ static bool CheckUnaryTypeTraitTypeCompleteness(Sema &S, TypeTrait UTT,
50325032
case UTT_IsArray:
50335033
case UTT_IsBoundedArray:
50345034
case UTT_IsPointer:
5035-
case UTT_IsReferenceable:
50365035
case UTT_IsLvalueReference:
50375036
case UTT_IsRvalueReference:
50385037
case UTT_IsMemberFunctionPointer:
@@ -5679,8 +5678,6 @@ static bool EvaluateUnaryTypeTrait(Sema &Self, TypeTrait UTT,
56795678
return T.isTriviallyRelocatableType(C);
56805679
case UTT_IsBitwiseCloneable:
56815680
return T.isBitwiseCloneableType(C);
5682-
case UTT_IsReferenceable:
5683-
return T.isReferenceable();
56845681
case UTT_CanPassInRegs:
56855682
if (CXXRecordDecl *RD = T->getAsCXXRecordDecl(); RD && !T.hasQualifiers())
56865683
return RD->canPassInRegisters();

‎clang/lib/StaticAnalyzer/Core/ExprEngine.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -74,6 +74,7 @@
7474
#include "llvm/Support/ErrorHandling.h"
7575
#include "llvm/Support/GraphWriter.h"
7676
#include "llvm/Support/SaveAndRestore.h"
77+
#include "llvm/Support/TimeProfiler.h"
7778
#include "llvm/Support/raw_ostream.h"
7879
#include <cassert>
7980
#include <cstdint>
@@ -1031,6 +1032,7 @@ void ExprEngine::removeDead(ExplodedNode *Pred, ExplodedNodeSet &Out,
10311032
const LocationContext *LC,
10321033
const Stmt *DiagnosticStmt,
10331034
ProgramPoint::Kind K) {
1035+
llvm::TimeTraceScope TimeScope("ExprEngine::removeDead");
10341036
assert((K == ProgramPoint::PreStmtPurgeDeadSymbolsKind ||
10351037
ReferenceStmt == nullptr || isa<ReturnStmt>(ReferenceStmt))
10361038
&& "PostStmt is not generally supported by the SymbolReaper yet");

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