@@ -176,9 +176,12 @@ static DecodeStatus decodeSrcOp(MCInst &Inst, unsigned EncSize,
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// Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to
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// get register class. Used by SGPR only operands.
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- #define DECODE_OPERAND_REG_7 (RegClass, OpWidth ) \
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+ #define DECODE_OPERAND_SREG_7 (RegClass, OpWidth ) \
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DECODE_SrcOp (Decode##RegClass##RegisterClass, 7 , OpWidth, Imm, false , 0 )
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+ #define DECODE_OPERAND_SREG_8 (RegClass, OpWidth ) \
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+ DECODE_SrcOp (Decode##RegClass##RegisterClass, 8 , OpWidth, Imm, false , 0 )
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+
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// Decoder for registers. Imm(10-bit): Imm{7-0} is number of register,
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// Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC).
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// Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp.
@@ -270,20 +273,21 @@ DECODE_OPERAND_REG_8(VReg_384)
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DECODE_OPERAND_REG_8(VReg_512)
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DECODE_OPERAND_REG_8(VReg_1024)
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- DECODE_OPERAND_REG_7(SReg_32, OPW32)
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- DECODE_OPERAND_REG_7(SReg_32_XM0, OPW32)
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- DECODE_OPERAND_REG_7(SReg_32_XEXEC, OPW32)
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- DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32)
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- DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32)
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- DECODE_OPERAND_REG_7(SReg_64, OPW64)
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- DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64)
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- DECODE_OPERAND_REG_7(SReg_64_XEXEC_XNULL, OPW64)
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- DECODE_OPERAND_REG_7(SReg_96, OPW96)
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- DECODE_OPERAND_REG_7(SReg_128, OPW128)
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- DECODE_OPERAND_REG_7(SReg_128_XNULL, OPW128)
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- DECODE_OPERAND_REG_7(SReg_256, OPW256)
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- DECODE_OPERAND_REG_7(SReg_256_XNULL, OPW256)
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- DECODE_OPERAND_REG_7(SReg_512, OPW512)
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+ DECODE_OPERAND_SREG_7(SReg_32, OPW32)
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+ DECODE_OPERAND_SREG_7(SReg_32_XM0, OPW32)
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+ DECODE_OPERAND_SREG_7(SReg_32_XEXEC, OPW32)
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+ DECODE_OPERAND_SREG_7(SReg_32_XM0_XEXEC, OPW32)
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+ DECODE_OPERAND_SREG_7(SReg_32_XEXEC_HI, OPW32)
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+ DECODE_OPERAND_SREG_7(SReg_64_XEXEC, OPW64)
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+ DECODE_OPERAND_SREG_7(SReg_64_XEXEC_XNULL, OPW64)
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+ DECODE_OPERAND_SREG_7(SReg_96, OPW96)
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+ DECODE_OPERAND_SREG_7(SReg_128, OPW128)
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+ DECODE_OPERAND_SREG_7(SReg_128_XNULL, OPW128)
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+ DECODE_OPERAND_SREG_7(SReg_256, OPW256)
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+ DECODE_OPERAND_SREG_7(SReg_256_XNULL, OPW256)
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+ DECODE_OPERAND_SREG_7(SReg_512, OPW512)
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+
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+ DECODE_OPERAND_SREG_8(SReg_64, OPW64)
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DECODE_OPERAND_REG_8(AGPR_32)
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DECODE_OPERAND_REG_8(AReg_64)
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