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[AMDGPU][MC] Don't crash on decoding invalid SOP1 ssrc0 operands. (llvm#130302)
These are encoded as 8-bit fields.
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3 files changed

+25
-15
lines changed

3 files changed

+25
-15
lines changed

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 19 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -176,9 +176,12 @@ static DecodeStatus decodeSrcOp(MCInst &Inst, unsigned EncSize,
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// Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to
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// get register class. Used by SGPR only operands.
179-
#define DECODE_OPERAND_REG_7(RegClass, OpWidth) \
179+
#define DECODE_OPERAND_SREG_7(RegClass, OpWidth) \
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DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)
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182+
#define DECODE_OPERAND_SREG_8(RegClass, OpWidth) \
183+
DECODE_SrcOp(Decode##RegClass##RegisterClass, 8, OpWidth, Imm, false, 0)
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// Decoder for registers. Imm(10-bit): Imm{7-0} is number of register,
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// Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC).
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// Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp.
@@ -270,20 +273,21 @@ DECODE_OPERAND_REG_8(VReg_384)
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DECODE_OPERAND_REG_8(VReg_512)
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DECODE_OPERAND_REG_8(VReg_1024)
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273-
DECODE_OPERAND_REG_7(SReg_32, OPW32)
274-
DECODE_OPERAND_REG_7(SReg_32_XM0, OPW32)
275-
DECODE_OPERAND_REG_7(SReg_32_XEXEC, OPW32)
276-
DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32)
277-
DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32)
278-
DECODE_OPERAND_REG_7(SReg_64, OPW64)
279-
DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64)
280-
DECODE_OPERAND_REG_7(SReg_64_XEXEC_XNULL, OPW64)
281-
DECODE_OPERAND_REG_7(SReg_96, OPW96)
282-
DECODE_OPERAND_REG_7(SReg_128, OPW128)
283-
DECODE_OPERAND_REG_7(SReg_128_XNULL, OPW128)
284-
DECODE_OPERAND_REG_7(SReg_256, OPW256)
285-
DECODE_OPERAND_REG_7(SReg_256_XNULL, OPW256)
286-
DECODE_OPERAND_REG_7(SReg_512, OPW512)
276+
DECODE_OPERAND_SREG_7(SReg_32, OPW32)
277+
DECODE_OPERAND_SREG_7(SReg_32_XM0, OPW32)
278+
DECODE_OPERAND_SREG_7(SReg_32_XEXEC, OPW32)
279+
DECODE_OPERAND_SREG_7(SReg_32_XM0_XEXEC, OPW32)
280+
DECODE_OPERAND_SREG_7(SReg_32_XEXEC_HI, OPW32)
281+
DECODE_OPERAND_SREG_7(SReg_64_XEXEC, OPW64)
282+
DECODE_OPERAND_SREG_7(SReg_64_XEXEC_XNULL, OPW64)
283+
DECODE_OPERAND_SREG_7(SReg_96, OPW96)
284+
DECODE_OPERAND_SREG_7(SReg_128, OPW128)
285+
DECODE_OPERAND_SREG_7(SReg_128_XNULL, OPW128)
286+
DECODE_OPERAND_SREG_7(SReg_256, OPW256)
287+
DECODE_OPERAND_SREG_7(SReg_256_XNULL, OPW256)
288+
DECODE_OPERAND_SREG_7(SReg_512, OPW512)
289+
290+
DECODE_OPERAND_SREG_8(SReg_64, OPW64)
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288292
DECODE_OPERAND_REG_8(AGPR_32)
289293
DECODE_OPERAND_REG_8(AReg_64)

llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sop1.txt

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2548,6 +2548,9 @@
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# GFX11: s_setpc_b64 vcc ; encoding: [0x6a,0x48,0x80,0xbe]
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0x6a,0x48,0x80,0xbe
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2551+
# GFX11: s_setpc_b64 -11/*Invalid immediate*/ ; encoding: [0xf5,0x48,0x80,0xbe]
2552+
0xcb,0x48,0xf5,0xbe
2553+
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# GFX11: s_sext_i32_i16 exec_hi, s1 ; encoding: [0x01,0x0f,0xff,0xbe]
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0x01,0x0f,0xff,0xbe
25532556

llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3267,6 +3267,9 @@
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# GFX12: s_setpc_b64 vcc ; encoding: [0x6a,0x48,0x80,0xbe]
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0x6a,0x48,0x80,0xbe
32693269

3270+
# GFX12: s_setpc_b64 -11/*Invalid immediate*/ ; encoding: [0xf5,0x48,0x80,0xbe]
3271+
0xcb,0x48,0xf5,0xbe
3272+
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# GFX12: s_sext_i32_i16 exec_hi, s1 ; encoding: [0x01,0x0f,0xff,0xbe]
32713274
0x01,0x0f,0xff,0xbe
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