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[RISCV] Change the vendor prefix for Rivos from "rv." to "ri." (llvm#128761)
There had been concern raised about possible confusion with "rvv". After internal discussion, we decided to go with an alternate prefix to reduce possible confusion going forward. The specification document (https://github.com/rivosinc/rivos-custom-extensions) has been updated. And also add the XRivosVizip extension to the documentation. I'd missed that in the initial commit.
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‎llvm/docs/RISCVUsage.rst

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@@ -468,6 +468,9 @@ The current vendor extensions supported are:
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``Xmipslsp``
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LLVM implements load/store pair instructions for the `p8700 processor <https://mips.com/products/hardware/p8700/>` by MIPS.
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``experimental-XRivosVizip``
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LLVM implements `version 0.1 of the Rivos Vector Register Zips extension specification <https://github.com/rivosinc/rivos-custom-extensions>`__.
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Experimental C Intrinsics
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=========================
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‎llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td

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@@ -18,10 +18,10 @@
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let Predicates = [HasVendorXRivosVizip], DecoderNamespace = "XRivos",
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Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather,
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Inst<6-0> = OPC_CUSTOM_2.Value in {
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defm RV_VZIPEVEN_V : VALU_IV_V<"rv.vzipeven", 0b001100>;
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defm RV_VZIPODD_V : VALU_IV_V<"rv.vzipodd", 0b011100>;
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defm RV_VZIP2A_V : VALU_IV_V<"rv.vzip2a", 0b000100>;
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defm RV_VZIP2B_V : VALU_IV_V<"rv.vzip2b", 0b010100>;
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defm RV_VUNZIP2A_V : VALU_IV_V<"rv.vunzip2a", 0b001000>;
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defm RV_VUNZIP2B_V : VALU_IV_V<"rv.vunzip2b", 0b011000>;
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defm RI_VZIPEVEN_V : VALU_IV_V<"ri.vzipeven", 0b001100>;
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defm RI_VZIPODD_V : VALU_IV_V<"ri.vzipodd", 0b011100>;
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defm RI_VZIP2A_V : VALU_IV_V<"ri.vzip2a", 0b000100>;
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defm RI_VZIP2B_V : VALU_IV_V<"ri.vzip2b", 0b010100>;
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defm RI_VUNZIP2A_V : VALU_IV_V<"ri.vunzip2a", 0b001000>;
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defm RI_VUNZIP2B_V : VALU_IV_V<"ri.vunzip2b", 0b011000>;
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}

‎llvm/test/MC/RISCV/xrivosvizip-invalid.s

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@@ -3,8 +3,8 @@
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# Disallowed source/dest overlap cases
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# CHECK: error: the destination vector register group cannot overlap the source vector register group
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rv.vzipeven.vv v2, v2, v3
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ri.vzipeven.vv v2, v2, v3
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# CHECK: error: the destination vector register group cannot overlap the source vector register group
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rv.vzipeven.vv v3, v2, v3
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ri.vzipeven.vv v3, v2, v3
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# CHECK: error: the destination vector register group cannot overlap the mask register
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rv.vzipeven.vv v0, v2, v3, v0.t
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ri.vzipeven.vv v0, v2, v3, v0.t

‎llvm/test/MC/RISCV/xrivosvizip-valid.s

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@@ -9,51 +9,51 @@
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# RUN: | llvm-objdump --mattr=+experimental-xrivosvizip -M no-aliases -d -r - \
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# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
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# CHECK-ASM-AND-OBJ: rv.vzipeven.vv v1, v2, v3
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# CHECK-ASM-AND-OBJ: ri.vzipeven.vv v1, v2, v3
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x32]
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rv.vzipeven.vv v1, v2, v3
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# CHECK-ASM-AND-OBJ: rv.vzipeven.vv v1, v2, v3, v0.t
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ri.vzipeven.vv v1, v2, v3
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# CHECK-ASM-AND-OBJ: ri.vzipeven.vv v1, v2, v3, v0.t
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x30]
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rv.vzipeven.vv v1, v2, v3, v0.t
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# CHECK-ASM-AND-OBJ: rv.vzipodd.vv v1, v2, v3
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ri.vzipeven.vv v1, v2, v3, v0.t
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# CHECK-ASM-AND-OBJ: ri.vzipodd.vv v1, v2, v3
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x72]
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rv.vzipodd.vv v1, v2, v3
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# CHECK-ASM-AND-OBJ: rv.vzipodd.vv v1, v2, v3, v0.t
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ri.vzipodd.vv v1, v2, v3
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# CHECK-ASM-AND-OBJ: ri.vzipodd.vv v1, v2, v3, v0.t
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x70]
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rv.vzipodd.vv v1, v2, v3, v0.t
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ri.vzipodd.vv v1, v2, v3, v0.t
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# CHECK-ASM-AND-OBJ: rv.vzip2a.vv v1, v2, v3
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# CHECK-ASM-AND-OBJ: ri.vzip2a.vv v1, v2, v3
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x12]
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rv.vzip2a.vv v1, v2, v3
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# CHECK-ASM-AND-OBJ: rv.vzip2a.vv v1, v2, v3, v0.t
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ri.vzip2a.vv v1, v2, v3
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# CHECK-ASM-AND-OBJ: ri.vzip2a.vv v1, v2, v3, v0.t
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x10]
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rv.vzip2a.vv v1, v2, v3, v0.t
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# CHECK-ASM-AND-OBJ: rv.vzip2b.vv v1, v2, v3
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ri.vzip2a.vv v1, v2, v3, v0.t
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# CHECK-ASM-AND-OBJ: ri.vzip2b.vv v1, v2, v3
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x52]
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rv.vzip2b.vv v1, v2, v3
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# CHECK-ASM-AND-OBJ: rv.vzip2b.vv v1, v2, v3, v0.t
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ri.vzip2b.vv v1, v2, v3
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# CHECK-ASM-AND-OBJ: ri.vzip2b.vv v1, v2, v3, v0.t
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x50]
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rv.vzip2b.vv v1, v2, v3, v0.t
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ri.vzip2b.vv v1, v2, v3, v0.t
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# CHECK-ASM-AND-OBJ: rv.vunzip2a.vv v1, v2, v3
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# CHECK-ASM-AND-OBJ: ri.vunzip2a.vv v1, v2, v3
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x22]
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rv.vunzip2a.vv v1, v2, v3
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# CHECK-ASM-AND-OBJ: rv.vunzip2a.vv v1, v2, v3, v0.t
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ri.vunzip2a.vv v1, v2, v3
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# CHECK-ASM-AND-OBJ: ri.vunzip2a.vv v1, v2, v3, v0.t
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x20]
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rv.vunzip2a.vv v1, v2, v3, v0.t
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# CHECK-ASM-AND-OBJ: rv.vunzip2b.vv v1, v2, v3
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ri.vunzip2a.vv v1, v2, v3, v0.t
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# CHECK-ASM-AND-OBJ: ri.vunzip2b.vv v1, v2, v3
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x62]
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rv.vunzip2b.vv v1, v2, v3
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# CHECK-ASM-AND-OBJ: rv.vunzip2b.vv v1, v2, v3, v0.t
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ri.vunzip2b.vv v1, v2, v3
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# CHECK-ASM-AND-OBJ: ri.vunzip2b.vv v1, v2, v3, v0.t
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x60]
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rv.vunzip2b.vv v1, v2, v3, v0.t
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ri.vunzip2b.vv v1, v2, v3, v0.t
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# Overlap between source registers *is* allowed
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# CHECK-ASM-AND-OBJ: rv.vzipeven.vv v1, v2, v2
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# CHECK-ASM-AND-OBJ: ri.vzipeven.vv v1, v2, v2
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# CHECK-ASM: encoding: [0xdb,0x00,0x21,0x32]
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rv.vzipeven.vv v1, v2, v2
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ri.vzipeven.vv v1, v2, v2
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# CHECK-ASM-AND-OBJ: rv.vzipeven.vv v1, v2, v0, v0.t
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# CHECK-ASM-AND-OBJ: ri.vzipeven.vv v1, v2, v0, v0.t
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# CHECK-ASM: encoding: [0xdb,0x00,0x20,0x30]
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rv.vzipeven.vv v1, v2, v0, v0.t
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ri.vzipeven.vv v1, v2, v0, v0.t

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