`mcause` error when load data

[ha0lyu]

Before start

• I have read the RISC-V ISA Manual and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册，这不是一个指令集本身的问题。
• I have read the XiangShan Documents. 我已经阅读过香山文档。
• I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。
• I have reviewed the commit messages from the relevant commit history. 我已经浏览过相关的提交历史和提交信息。
• I have reproduced the incorrect behaviors using the latest commit on the master branch. 我已经使用 master 分支最新的 commit 复现了不正确的行为。

Describe the bug

I have no idea why it happened:

[28] commit pc 0000000080001000 inst 0280006f wen 0 dst 00 data 0000000000000000 idx 017 j       pc + 0x28
[29] commit pc 0000000080001028 inst b850d617 wen 1 dst 12 data 000000003850e028 idx 018 auipc   a2, 0xb850d
[30] commit pc 000000008000102c inst bee03893 wen 1 dst 17 data 0000000000000001 idx 019 sltiu   a7, zero, -1042
[31] exception pc 0000000080001030 inst 000fb083 cause 0000000000000013 ld      ra, 0(t6) <--
......
privilegeMode: 3
 mcause different at pc = 0x0080001028, right= 0x0000000000000005, wrong = 0x0000000000000013
Core 0: �[31mABORT at pc = 0x8000104c

Please check the log file for more information.

Expected behavior

The mcause should be 0x05.

To Reproduce

test.zip

Environment

• XiangShan branch: master
• XiangShan commit id: c25dcc6
• XiangShan config: MinimalConfig
• Ready2run: 31254e6

Additional context

If I missed something, or I made mistakes, please tell me. Thanks.

[ha0lyu]

I am sorry. I made a mistake.
There are two xiangshan env: xs-new & xs-env on my system. The xs-new is not the latest one, and I met difference on this env first. When I check this difference on the latest env xs-env, I ran: ./build/emu -C 10000 -i /home/test.elf--diff=/home/xs-new/XiangShan/ready-to-run/riscv64-nemu-interpreter-so --dump-commit-trace 2>/d ev/nullclear 1>./test.log under xs-env path. This is the reason why it happened.
I retest this test case in a clearly new system. However, a new difference occurred:

==============  Store Commit Event (Core 0)  ==============
Mismatch for store commits 
  REF commits addr 0x0000000080004258, data 0x8000000200046100, mask 0x00ff, pc 0x0000000000000000
  DUT commits addr 0x0000000080004258, data 0x8000000200046100, mask 0x00ff, pc 0x0000000080001188, robidx 0x27
Core 0: �[31mABORT at pc = 0x800011b4

Here is the new log file.
test.log

• XiangShan branch: master
• XiangShan commit id: c25dcc6
• XiangShan config: MinimalConfig
• Ready2run: 31254e6

[cz4e]

I tried the following:

• XiangShan master: c25dcc6
• XiangShan config: MinimalConfig
• ready-to-run: 31254e6
• compile options: 1) make emu CONFIG=MinimalConfig EMU_THREADS=8 EMU_TRACE=1 -j64; 2) make emu CONFIG=MinimalConfig EMU_THREADS=8 -j64

Results:

• 1. options passed; 2) failed
• this issue needs further investigation
• It is recommended to use DefaultConfig or KunminghuV2Config

[ha0lyu]

Hi @cz4e, thanks for reply.
I forgot to write how to make. Can you try make emu CONFIG=MinimalConfig -j40 again?

[cz4e]

I tried. Option 2 is the same as your compilation.

I tried different compilation options, such as the two mentioned above. EMU passed when EMU_TRACE was used. After remove EMU_TRACE , EMU failed. This doesn't seem to be a RTL issue. Please wait for reply.