v0.2.0

New

• Implement decoder generator for variable-length instructions (#291) @rascmatt
• asm: Emit correct kind of relocations for unknown symbols (#221) @benjaminkasper99
• ast: Add default recursive visitor and refactor AstDumper (#157) @flofriday
• ast: Allow machine instructions in abi as special instruction (#287) @kper
• ci: Added aarch64 images (#266) @kper
• ci: Added image QEMU riscv64 (#218) @kper
• ci: Merge QEMU images together (#271) @kper
• decode: Extract and evaluate format fields from encoding (#272) @rascmatt
• decoder: Extend CLI to switch between decoder genereators (#358) @rascmatt
• decoder: Support subsumed instructions in irregular VDT generator (#318) @rascmatt
• embench: Setup embench for riscv64 (#228) @kper
• frontend+viam+lcb: Add format field access predicate and encoding (#324) @Jozott00
• frontend: Add [ htif ] annotation (#261) @Jozott00
• frontend: Add [ zero ] annotation to alias register definition (#292) @Jozott00
• frontend: Add annotation support (#182) @flofriday
• frontend: Add exception definition support (#160) @Jozott00
• frontend: Add tensor types (#340) @flofriday
• frontend: Refactor symbol collecting (#176) @flofriday
• frontend: Rename ExtendId and IdToStr to AsId and AsStr (#314) @flofriday
• frontend: Replace register file by register (#195) @Jozott00
• frontend: Support multi-inheritance on ISA definitions (#238) @Jozott00
• frontend: Support register file instances in callee saved/caller saved ABI definitions (#285) @kper
• frontend: Support slices on assignments (#246) @Jozott00
• gcb: Implemented edge case pruning when raising exception (#171) @kper
• grammar: Rename micro processor to processor (#205) @Jozott00
• iss: Add [undefined when] annotation (#345) @Jozott00
• iss: Add memory region to processor (discussion #138) (#212) @Jozott00
• iss: Add processor reset definition (discussion: #138) (#210) @Jozott00
• iss: Add exception support (#169) @Jozott00
• iss: Generate one translation file per ISA specification (#159) @Jozott00
• iss: Initial cosimulation runner (#290) @Giftzwerg02
• iss: Optimize selects with constant condition (#343) @Jozott00
• iss: Support rv32csr.vadl specification (#223) @Jozott00
• language: Add CTZ and CTO built-ins (#279) @Jozott00
• lcb: Allow multiple fields in decoding function (#350) @kper
• lcb: Bug fixes for aarch64 (#361) @kper
• lcb: Eliminate register writes (#363) @kper
• lcb: Extend MCInstExpander (#353) @kper
• lcb: Implemented plt suffix for calls when PIC (#207) @kper
• lcb: Migrated spike to qemu for riscv32 (#302) @kper
• lcb: Print pseudo instructions (#204) @kper
• lcb: Printed InstAlias (#203) @kper
• lcb: Refactored test execution (#313) @kper
• lcb: Refactored uses and defs of register (#362) @kper
• lcb: Run the optimizer on derived graphs and enhance dumps (#250) @kper
• lcb: Setup qemu test image for lcb execution (#220) @kper
• lcb: Upgrade llvm19.1.7 (#235) @kper
• lcb: Use lcb-test-base as new base image for execution tests (#276) @kper
• parser: Add record returns to models (#306) @flofriday
• parser: Improve suggestions for unknown symbol errors (#275) @flofriday
• parser: Rank suggestions for invalid syntax types error message based on edit distance. (#258) @flofriday
• parser: Refactor symbol resolver (#180) @flofriday
• rtl: Map and inline instruction behavior to MiA description (#273) @linushdot
• typechecker: Add suggestions to invalid type errors (#280) @flofriday
• vdt: Add encoding constraint (#320) @Jozott00
• viam: Added algebraic simplifications (#155) @kper
• viam: Keep source code location when copy (#360) @kper

Bug Fixes

• Fixing regressions in master (#296) @kper
• ast: Fixed error message when pseudo instruction was not found (#168) @kper
• decode: Remove usage of irregular decoder generator (#298) @rascmatt
• decoder: Fix issues with split bit splices encoding (#237) @rascmatt
• embench: Fixed paths after renaming (#256) @kper
• embench: WIP to support riscv64im (#179) @kper
• frontend: Fix assembly with multiple instructions (#328) @flofriday
• frontend: Fix pretty print (#243) @Jozott00
• frontend: Support slices on assignments (#246) @Jozott00
• iss: Fix CPU state register overflow (#348) @Jozott00
• iss: Fix ROR built-in (#355) @Jozott00
• lcb: #331 crash during varrisc (#332) @kper
• lcb: Defined test macros LP64 and __LP64 (#295) @kper
• lcb: Fix #333 (#334) @kper
• lcb: Fix pseudo expansion decoding and assembly printer encoding (#189) @benjaminkasper99
• lcb: Fix riscv64 embench (#253) @kper
• lcb: Fixed RISCV64 execution tests (#213) @kper
• lcb: Fixed wikisort benchmark (#249) @kper
• lcb: Handle RET and DagToISel zero register optimisation (#335) @kper
• lcb: Make plt based on isPositionIndepedent (#347) @kper
• lcb: Refactored predicates (#367) @kper
• lcb: Remove isReMaterializable and isAsCheapAsAMove for jump instrs (#368) @benedikt-l-huber
• lcb: Removed warning (#369) @kper
• lowering: Convert crash to error when calling pseudo instructions (#339) @flofriday
• parser: Fix crash with annotations on encodings (#317) @flofriday
• parser: Fix empty identifiers (#303) @flofriday
• parser: Fix inherit records from extended ISA (#308) @flofriday
• parser: Fix nested let statement with let expression (#336) @flofriday
• parser: Improve macro reliency (#251) @flofriday
• spec: Updated calling convention (#322) @kper
• sys/aarch64.vadl: Fix MRS nzcv shift (#309) @Jozott00
• sys:var-risc Fix opcode encoding of SYS insn (#234) @rascmatt
• typechecker: Fix crash typechecking enum field before enum definition (#214) @flofriday
• typechecker: Fix crash when symbol points to definition that isn't a expr (#170) @flofriday
• typechecker: Fix crash with invalid range in format field (#327) @flofriday
• typechecker: Fix crash with zero bitwidth (#172) @flofriday
• typechecker: Fix skipping imported specs (#329) @flofriday
• typechecker: Fix wrong long multiply type (#321) @flofriday
• viam: Allow multiple field references in FieldAccess (#259) @Jozott00

Full Changelog: v0.1.0...v0.2.0