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Releases: OpenVADL/openvadl

v0.2.0

25 Jun 10:33
03e3c79

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New

  • Implement decoder generator for variable-length instructions (#291) @rascmatt
  • asm: Emit correct kind of relocations for unknown symbols (#221) @benjaminkasper99
  • ast: Add default recursive visitor and refactor AstDumper (#157) @flofriday
  • ast: Allow machine instructions in abi as special instruction (#287) @kper
  • ci: Added aarch64 images (#266) @kper
  • ci: Added image QEMU riscv64 (#218) @kper
  • ci: Merge QEMU images together (#271) @kper
  • decode: Extract and evaluate format fields from encoding (#272) @rascmatt
  • decoder: Extend CLI to switch between decoder genereators (#358) @rascmatt
  • decoder: Support subsumed instructions in irregular VDT generator (#318) @rascmatt
  • embench: Setup embench for riscv64 (#228) @kper
  • frontend+viam+lcb: Add format field access predicate and encoding (#324) @Jozott00
  • frontend: Add [ htif ] annotation (#261) @Jozott00
  • frontend: Add [ zero ] annotation to alias register definition (#292) @Jozott00
  • frontend: Add annotation support (#182) @flofriday
  • frontend: Add exception definition support (#160) @Jozott00
  • frontend: Add tensor types (#340) @flofriday
  • frontend: Refactor symbol collecting (#176) @flofriday
  • frontend: Rename ExtendId and IdToStr to AsId and AsStr (#314) @flofriday
  • frontend: Replace register file by register (#195) @Jozott00
  • frontend: Support multi-inheritance on ISA definitions (#238) @Jozott00
  • frontend: Support register file instances in callee saved/caller saved ABI definitions (#285) @kper
  • frontend: Support slices on assignments (#246) @Jozott00
  • gcb: Implemented edge case pruning when raising exception (#171) @kper
  • grammar: Rename micro processor to processor (#205) @Jozott00
  • iss: Add [undefined when] annotation (#345) @Jozott00
  • iss: Add memory region to processor (discussion #138) (#212) @Jozott00
  • iss: Add processor reset definition (discussion: #138) (#210) @Jozott00
  • iss: Add exception support (#169) @Jozott00
  • iss: Generate one translation file per ISA specification (#159) @Jozott00
  • iss: Initial cosimulation runner (#290) @Giftzwerg02
  • iss: Optimize selects with constant condition (#343) @Jozott00
  • iss: Support rv32csr.vadl specification (#223) @Jozott00
  • language: Add CTZ and CTO built-ins (#279) @Jozott00
  • lcb: Allow multiple fields in decoding function (#350) @kper
  • lcb: Bug fixes for aarch64 (#361) @kper
  • lcb: Eliminate register writes (#363) @kper
  • lcb: Extend MCInstExpander (#353) @kper
  • lcb: Implemented plt suffix for calls when PIC (#207) @kper
  • lcb: Migrated spike to qemu for riscv32 (#302) @kper
  • lcb: Print pseudo instructions (#204) @kper
  • lcb: Printed InstAlias (#203) @kper
  • lcb: Refactored test execution (#313) @kper
  • lcb: Refactored uses and defs of register (#362) @kper
  • lcb: Run the optimizer on derived graphs and enhance dumps (#250) @kper
  • lcb: Setup qemu test image for lcb execution (#220) @kper
  • lcb: Upgrade llvm19.1.7 (#235) @kper
  • lcb: Use lcb-test-base as new base image for execution tests (#276) @kper
  • parser: Add record returns to models (#306) @flofriday
  • parser: Improve suggestions for unknown symbol errors (#275) @flofriday
  • parser: Rank suggestions for invalid syntax types error message based on edit distance. (#258) @flofriday
  • parser: Refactor symbol resolver (#180) @flofriday
  • rtl: Map and inline instruction behavior to MiA description (#273) @linushdot
  • typechecker: Add suggestions to invalid type errors (#280) @flofriday
  • vdt: Add encoding constraint (#320) @Jozott00
  • viam: Added algebraic simplifications (#155) @kper
  • viam: Keep source code location when copy (#360) @kper

Bug Fixes

Full Changelog: v0.1.0...v0.2.0

v0.1.0

11 Apr 13:28
279e6d9

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New

  • Change binary literal to return constant type (#146) @flofriday
  • asm: Support binary encoding of immediate operands (#124) @benjaminkasper99
  • frontend+lcb: Implemented ABI address load specification and relocations (#123) @kper
  • frontend: Add alias definitions (#83) @flofriday
  • frontend: Add bits concatenation (#48) @flofriday
  • frontend: Add status flags, bools in bit concatination and match statement (#94) @flofriday
  • gcb: Extend labeling with types (#100) @kper
  • iss: Optimize generated ISS and extend CLI to skip optimizations (#64) @Jozott00
  • iss: Optimize load and stores (#89) @Jozott00
  • iss: Set the generated machine to be the default (#150) @Jozott00
  • iss: Support firmware definition in processor (#133) @Jozott00
  • lcb: Added register adjustment (#93) @kper
  • lcb: Emit correct llvm relocations (#136) @benjaminkasper99
  • lcb: Handle signed and unsigned const mat #129 (#131) @kper
  • lcb: Implement constant materialization for riscv64 (#134) @kper
  • lcb: Implemented PIC support (#139) @kper
  • lcb: Implemented automatic deriving of setOperationAction (#101) @kper
  • lcb: Implemented constant sequences (#91) @kper
  • lcb: Implemented support for constant sequences (#86) @kper
  • lcb: Instruction pattern pruning for edge cases (#7) @kper
  • lcb: Setup embench for riscv64 (#142) @kper
  • lcb: Support multiple immediates and field access functions (#77) @kper
  • lowering: Add raise, alias, register write, match statement and fix call expression (#108) @flofriday
  • parser: Improve error messages from the parser (#9) @flofriday
  • typechecker: Add checks for infinite recursion (#117) @flofriday
  • typechecker: Implement new semantics for constant branches (#78) @flofriday
  • viam: Add ArtificialResource, Procedure and Exception definitions (#27) @Jozott00
  • viam: Add pretty print to definitions (#143) @flofriday
  • viam: Add status built-in inlining pass (#24) @Jozott00

Bug Fixes