@@ -363,25 +363,6 @@ u32 i = 0;
363363                while  (((* SCState ) !=  SC_POWER_OFF ) &&  ((* SCState ) !=  SC_ACTIVE ))
364364                {
365365                    SC_AnswerReq  (SCState , & SC_ATR_Table [0 ], 40 );   /* Check for answer to eeset */ 
366-                     if  (SC_ATR_Table [2 ] ==  0x96 ){
367-                         // patch PPS byte for HSM v4 
368-                         //                    hsm2_ATR[2] = 0x04; // works,  RSA4k 84.16 sec, 77419.3548387097 bps 
369-                         // hsm2_ATR[2] = 0x39; // works,  RSA4k 47.75 secs, 96774.1935483871 bps 
370-                         // hsm2_ATR[2] = 0x99; // fails,  140625 bps 
371-                         // hsm2_ATR[2] = 0x95; // fails,  112500 bps 
372-                         // SC_ATR_Table[2]= 0x39; // works on HW3, on v0.7-based firmware, but fails on HW4 for some reason 
373-                         // SC_ATR_Table[2]= 0x04; yes 
374-                         // SC_ATR_Table[2]= 0x11; yes 
375-                         // SC_ATR_Table[2]= 0xA9; nope 
376-                         // SC_ATR_Table[2]= 0xB9; //yes, 70,312.50 
377- //                        SC_ATR_Table[2]= 0x98; //yes, 84,375.00 
378-                         // SC_ATR_Table[2]= 0xA9; //nope, 93,750.00 
379-                         // SC_ATR_Table[2]= 0xD7; //nope, 112,500.00 
380-                         // SC_ATR_Table[2]= 0x46; // nope, 103,225.81 
381-                         // SC_ATR_Table[2]= 0x39; //nope, 96,774.19 
382-                         // SC_ATR_Table[2]= 0x46; //nope, 103,225.81 
383-                         // SC_ATR_Table[2]= 0x28; //yes, 77,419.35 
384-                     }
385366                }
386367            }
387368            break ;
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