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‎CHANGELOG.md

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@@ -2,6 +2,8 @@
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## Release 535 Entries
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### [535.104.12] 2023-09-25
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### [535.104.05] 2023-08-22
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### [535.98] 2023-08-08

‎README.md

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# NVIDIA Linux Open GPU Kernel Module Source
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This is the source release of the NVIDIA Linux open GPU kernel modules,
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version 535.104.05.
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version 535.104.12.
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## How to Build
@@ -17,7 +17,7 @@ as root:
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Note that the kernel modules built here must be used with GSP
1919
firmware and user-space NVIDIA GPU driver components from a corresponding
20-
535.104.05 driver release. This can be achieved by installing
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535.104.12 driver release. This can be achieved by installing
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the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
2222
option. E.g.,
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@@ -180,15 +180,15 @@ software applications.
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## Compatible GPUs
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182182
The open-gpu-kernel-modules can be used on any Turing or later GPU
183-
(see the table below). However, in the 535.104.05 release,
183+
(see the table below). However, in the 535.104.12 release,
184184
GeForce and Workstation support is still considered alpha-quality.
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186186
To enable use of the open kernel modules on GeForce and Workstation GPUs,
187187
set the "NVreg_OpenRmEnableUnsupportedGpus" nvidia.ko kernel module
188188
parameter to 1. For more details, see the NVIDIA GPU driver end user
189189
README here:
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191-
https://us.download.nvidia.com/XFree86/Linux-x86_64/535.104.05/README/kernel_open.html
191+
https://us.download.nvidia.com/XFree86/Linux-x86_64/535.104.12/README/kernel_open.html
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In the below table, if three IDs are listed, the first is the PCI Device
194194
ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI
@@ -856,6 +856,10 @@ Subsystem Device ID.
856856
| NVIDIA RTX 4000 SFF Ada Generation | 27B0 103C 16FA |
857857
| NVIDIA RTX 4000 SFF Ada Generation | 27B0 10DE 16FA |
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| NVIDIA RTX 4000 SFF Ada Generation | 27B0 17AA 16FA |
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| NVIDIA RTX 4500 Ada Generation | 27B1 1028 180C |
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| NVIDIA RTX 4500 Ada Generation | 27B1 103C 180C |
861+
| NVIDIA RTX 4500 Ada Generation | 27B1 10DE 180C |
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| NVIDIA RTX 4500 Ada Generation | 27B1 17AA 180C |
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| NVIDIA RTX 4000 Ada Generation | 27B2 1028 181B |
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| NVIDIA RTX 4000 Ada Generation | 27B2 103C 181B |
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| NVIDIA RTX 4000 Ada Generation | 27B2 10DE 181B |

‎kernel-open/Kbuild

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@@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc
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EXTRA_CFLAGS += -I$(src)
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EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args
7474
EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
75-
EXTRA_CFLAGS += -DNV_VERSION_STRING=\"535.104.05\"
75+
EXTRA_CFLAGS += -DNV_VERSION_STRING=\"535.104.12\"
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ifneq ($(SYSSRCHOST1X),)
7878
EXTRA_CFLAGS += -I$(SYSSRCHOST1X)

‎kernel-open/conftest.sh

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@@ -5743,23 +5743,25 @@ compile_test() {
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compile_check_conftest "$CODE" "NV_IOASID_GET_PRESENT" "" "functions"
57445744
;;
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5746-
mm_pasid_set)
5746+
mm_pasid_drop)
57475747
#
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# Determine if mm_pasid_set() function is present
5748+
# Determine if mm_pasid_drop() function is present
5749+
#
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# Added by commit 701fac40384f ("iommu/sva: Assign a PASID to mm
5751+
# on PASID allocation and free it on mm exit") in v5.18.
5752+
# Moved to linux/iommu.h in commit cd3891158a77 ("iommu/sva: Move
5753+
# PASID helpers to sva code") in v6.4.
57495754
#
5750-
# mm_pasid_set() function was added by commit
5751-
# 701fac40384f07197b106136012804c3cae0b3de (iommu/sva: Assign a
5752-
# PASID to mm on PASID allocation and free it on mm exit) in v5.18.
5753-
# (2022-02-15).
57545755
CODE="
57555756
#if defined(NV_LINUX_SCHED_MM_H_PRESENT)
57565757
#include <linux/sched/mm.h>
57575758
#endif
5758-
void conftest_mm_pasid_set(void) {
5759-
mm_pasid_set();
5759+
#include <linux/iommu.h>
5760+
void conftest_mm_pasid_drop(void) {
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mm_pasid_drop();
57605762
}"
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5762-
compile_check_conftest "$CODE" "NV_MM_PASID_SET_PRESENT" "" "functions"
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compile_check_conftest "$CODE" "NV_MM_PASID_DROP_PRESENT" "" "functions"
57635765
;;
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57655767
drm_crtc_state_has_no_vblank)

‎kernel-open/nvidia-uvm/nvidia-uvm.Kbuild

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@@ -81,7 +81,7 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += set_memory_uc
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NV_CONFTEST_FUNCTION_COMPILE_TESTS += set_pages_uc
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NV_CONFTEST_FUNCTION_COMPILE_TESTS += ktime_get_raw_ts64
8383
NV_CONFTEST_FUNCTION_COMPILE_TESTS += ioasid_get
84-
NV_CONFTEST_FUNCTION_COMPILE_TESTS += mm_pasid_set
84+
NV_CONFTEST_FUNCTION_COMPILE_TESTS += mm_pasid_drop
8585
NV_CONFTEST_FUNCTION_COMPILE_TESTS += migrate_vma_setup
8686
NV_CONFTEST_FUNCTION_COMPILE_TESTS += mmget_not_zero
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NV_CONFTEST_FUNCTION_COMPILE_TESTS += mmgrab

‎kernel-open/nvidia-uvm/uvm_ats_sva.h

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@@ -32,19 +32,23 @@
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// For ATS support on aarch64, arm_smmu_sva_bind() is needed for
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// iommu_sva_bind_device() calls. Unfortunately, arm_smmu_sva_bind() is not
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// conftest-able. We instead look for the presence of ioasid_get() or
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// mm_pasid_set(). ioasid_get() was added in the same patch series as
36-
// arm_smmu_sva_bind() and removed in v6.0. mm_pasid_set() was added in the
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// mm_pasid_drop(). ioasid_get() was added in the same patch series as
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// arm_smmu_sva_bind() and removed in v6.0. mm_pasid_drop() was added in the
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// same patch as the removal of ioasid_get(). We assume the presence of
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// arm_smmu_sva_bind() if ioasid_get(v5.11 - v5.17) or mm_pasid_set(v5.18+) is
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// arm_smmu_sva_bind() if ioasid_get(v5.11 - v5.17) or mm_pasid_drop(v5.18+) is
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// present.
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//
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// arm_smmu_sva_bind() was added with commit
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// 32784a9562fb0518b12e9797ee2aec52214adf6f and ioasid_get() was added with
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// commit cb4789b0d19ff231ce9f73376a023341300aed96 (11/23/2020). Commit
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// 701fac40384f07197b106136012804c3cae0b3de (02/15/2022) removed ioasid_get()
45-
// and added mm_pasid_set().
46-
#if UVM_CAN_USE_MMU_NOTIFIERS() && (defined(NV_IOASID_GET_PRESENT) || defined(NV_MM_PASID_SET_PRESENT))
47-
#define UVM_ATS_SVA_SUPPORTED() 1
45+
// and added mm_pasid_drop().
46+
#if UVM_CAN_USE_MMU_NOTIFIERS() && (defined(NV_IOASID_GET_PRESENT) || defined(NV_MM_PASID_DROP_PRESENT))
47+
#if defined(CONFIG_IOMMU_SVA)
48+
#define UVM_ATS_SVA_SUPPORTED() 1
49+
#else
50+
#define UVM_ATS_SVA_SUPPORTED() 0
51+
#endif
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#else
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#define UVM_ATS_SVA_SUPPORTED() 0
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#endif

‎src/common/inc/nvBldVer.h

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#endif
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#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
46-
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r537_13-260"
47-
#define NV_BUILD_CHANGELIST_NUM (33206197)
46+
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r537_13-267"
47+
#define NV_BUILD_CHANGELIST_NUM (33312039)
4848
#define NV_BUILD_TYPE "Official"
49-
#define NV_BUILD_NAME "rel/gpu_drv/r535/r537_13-260"
50-
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33206197)
49+
#define NV_BUILD_NAME "rel/gpu_drv/r535/r537_13-267"
50+
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33312039)
5151

5252
#else /* Windows builds */
53-
#define NV_BUILD_BRANCH_VERSION "r537_13-1"
54-
#define NV_BUILD_CHANGELIST_NUM (33194057)
53+
#define NV_BUILD_BRANCH_VERSION "r537_13-7"
54+
#define NV_BUILD_CHANGELIST_NUM (33274399)
5555
#define NV_BUILD_TYPE "Official"
56-
#define NV_BUILD_NAME "537.17"
57-
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33194057)
56+
#define NV_BUILD_NAME "537.39"
57+
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33274399)
5858
#define NV_BUILD_BRANCH_BASE_VERSION R535
5959
#endif
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// End buildmeister python edited section

‎src/common/inc/nvUnixVersion.h

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#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
55
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
66

7-
#define NV_VERSION_STRING "535.104.05"
7+
#define NV_VERSION_STRING "535.104.12"
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99
#else
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‎src/common/inc/swref/published/hopper/gh100/dev_fb.h

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2020
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
2121
* DEALINGS IN THE SOFTWARE.
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*/
23-
23+
2424
#ifndef __gh100_dev_fb_h_
2525
#define __gh100_dev_fb_h_
2626
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT 8 /* */
@@ -29,4 +29,25 @@
2929
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI 0x00100A38 /* RW-4R */
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#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
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#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */
32+
33+
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */
34+
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */
35+
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
36+
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
37+
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
38+
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
39+
40+
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */
41+
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */
42+
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
43+
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
44+
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
45+
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
46+
47+
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */
48+
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */
49+
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
50+
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
51+
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
52+
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
3253
#endif // __gh100_dev_fb_h_

‎src/common/inc/swref/published/hopper/gh100/dev_fbpa.h

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/*
2+
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
3+
* SPDX-License-Identifier: MIT
4+
*
5+
* Permission is hereby granted, free of charge, to any person obtaining a
6+
* copy of this software and associated documentation files (the "Software"),
7+
* to deal in the Software without restriction, including without limitation
8+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
9+
* and/or sell copies of the Software, and to permit persons to whom the
10+
* Software is furnished to do so, subject to the following conditions:
11+
*
12+
* The above copyright notice and this permission notice shall be included in
13+
* all copies or substantial portions of the Software.
14+
*
15+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18+
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20+
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21+
* DEALINGS IN THE SOFTWARE.
22+
*/
23+
24+
#ifndef __gh100_dev_fbpa_h_
25+
#define __gh100_dev_fbpa_h_
26+
27+
#define NV_PFB_FBPA_0_ECC_DED_COUNT__SIZE_1 4 /* */
28+
#define NV_PFB_FBPA_0_ECC_DED_COUNT(i) (0x009025A0+(i)*4) /* RW-4A */
29+
#endif // __gh100_dev_fbpa_h_

‎src/common/inc/swref/published/hopper/gh100/dev_ltc.h

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1+
/*
2+
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
3+
* SPDX-License-Identifier: MIT
4+
*
5+
* Permission is hereby granted, free of charge, to any person obtaining a
6+
* copy of this software and associated documentation files (the "Software"),
7+
* to deal in the Software without restriction, including without limitation
8+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
9+
* and/or sell copies of the Software, and to permit persons to whom the
10+
* Software is furnished to do so, subject to the following conditions:
11+
*
12+
* The above copyright notice and this permission notice shall be included in
13+
* all copies or substantial portions of the Software.
14+
*
15+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18+
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20+
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21+
* DEALINGS IN THE SOFTWARE.
22+
*/
23+
24+
#ifndef __gh100_dev_ltc_h_
25+
#define __gh100_dev_ltc_h_
26+
27+
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT 0x001404f8 /* RW-4R */
28+
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIVF */
29+
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */
30+
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIVF */
31+
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */
32+
33+
#endif // __gh100_dev_ltc_h_

‎src/common/inc/swref/published/hopper/gh100/dev_nv_xpl.h

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1+
/*
2+
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
3+
* SPDX-License-Identifier: MIT
4+
*
5+
* Permission is hereby granted, free of charge, to any person obtaining a
6+
* copy of this software and associated documentation files (the "Software"),
7+
* to deal in the Software without restriction, including without limitation
8+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
9+
* and/or sell copies of the Software, and to permit persons to whom the
10+
* Software is furnished to do so, subject to the following conditions:
11+
*
12+
* The above copyright notice and this permission notice shall be included in
13+
* all copies or substantial portions of the Software.
14+
*
15+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18+
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20+
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21+
* DEALINGS IN THE SOFTWARE.
22+
*/
23+
24+
#ifndef __gh100_dev_nv_xpl_h_
25+
#define __gh100_dev_nv_xpl_h_
26+
#define NV_XPL_DL_ERR_COUNT_RBUF 0x00000a54 /* R--4R */
27+
#define NV_XPL_DL_ERR_COUNT_RBUF__PRIV_LEVEL_MASK 0x00000b08 /* */
28+
#define NV_XPL_DL_ERR_COUNT_RBUF_CORR_ERR 15:0 /* R-EVF */
29+
#define NV_XPL_DL_ERR_COUNT_RBUF_CORR_ERR_INIT 0x0000 /* R-E-V */
30+
#define NV_XPL_DL_ERR_COUNT_RBUF_UNCORR_ERR 31:16 /* R-EVF */
31+
#define NV_XPL_DL_ERR_COUNT_RBUF_UNCORR_ERR_INIT 0x0000 /* R-E-V */
32+
#define NV_XPL_DL_ERR_COUNT_SEQ_LUT 0x00000a58 /* R--4R */
33+
#define NV_XPL_DL_ERR_COUNT_SEQ_LUT__PRIV_LEVEL_MASK 0x00000b08 /* */
34+
#define NV_XPL_DL_ERR_COUNT_SEQ_LUT_CORR_ERR 15:0 /* R-EVF */
35+
#define NV_XPL_DL_ERR_COUNT_SEQ_LUT_CORR_ERR_INIT 0x0000 /* R-E-V */
36+
#define NV_XPL_DL_ERR_COUNT_SEQ_LUT_UNCORR_ERR 31:16 /* R-EVF */
37+
#define NV_XPL_DL_ERR_COUNT_SEQ_LUT_UNCORR_ERR_INIT 0x0000 /* R-E-V */
38+
39+
#define NV_XPL_DL_ERR_RESET 0x00000a5c /* RW-4R */
40+
#define NV_XPL_DL_ERR_RESET_RBUF_CORR_ERR_COUNT 0:0 /* RWCVF */
41+
#define NV_XPL_DL_ERR_RESET_RBUF_CORR_ERR_COUNT_DONE 0x0 /* RWC-V */
42+
#define NV_XPL_DL_ERR_RESET_RBUF_CORR_ERR_COUNT_PENDING 0x1 /* -W--T */
43+
#define NV_XPL_DL_ERR_RESET_SEQ_LUT_CORR_ERR_COUNT 1:1 /* RWCVF */
44+
#define NV_XPL_DL_ERR_RESET_SEQ_LUT_CORR_ERR_COUNT_DONE 0x0 /* RWC-V */
45+
#define NV_XPL_DL_ERR_RESET_SEQ_LUT_CORR_ERR_COUNT_PENDING 0x1 /* -W--T */
46+
#define NV_XPL_DL_ERR_RESET_RBUF_UNCORR_ERR_COUNT 16:16 /* RWCVF */
47+
#define NV_XPL_DL_ERR_RESET_RBUF_UNCORR_ERR_COUNT_DONE 0x0 /* RWC-V */
48+
#define NV_XPL_DL_ERR_RESET_RBUF_UNCORR_ERR_COUNT_PENDING 0x1 /* -W--T */
49+
#define NV_XPL_DL_ERR_RESET_SEQ_LUT_UNCORR_ERR_COUNT 17:17 /* RWCVF */
50+
#define NV_XPL_DL_ERR_RESET_SEQ_LUT_UNCORR_ERR_COUNT_DONE 0x0 /* RWC-V */
51+
#define NV_XPL_DL_ERR_RESET_SEQ_LUT_UNCORR_ERR_COUNT_PENDING 0x1 /* -W--T */
52+
#endif // __gh100_dev_nv_xpl_h__

‎src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pri.h

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#ifndef __gh100_dev_xtl_ep_pri_h__
2525
#define __gh100_dev_xtl_ep_pri_h__
2626
#define NV_EP_PCFGM 0x92FFF:0x92000 /* RW--D */
27+
28+
#define NV_XTL_EP_PRI_DED_ERROR_STATUS 0x0000043C /* RW-4R */
29+
#define NV_XTL_EP_PRI_RAM_ERROR_INTR_STATUS 0x000003C8 /* RW-4R */
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#endif // __gh100_dev_xtl_ep_pri_h__

‎src/common/inc/swref/published/hopper/gh100/hwproject.h

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@@ -21,3 +21,9 @@
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* DEALINGS IN THE SOFTWARE.
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*/
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#define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS 52
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#define NV_LTC_PRI_STRIDE 8192
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#define NV_LTS_PRI_STRIDE 512
26+
#define NV_FBPA_PRI_STRIDE 16384
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#define NV_SCAL_LITTER_NUM_FBPAS 24
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#define NV_XPL_BASE_ADDRESS 540672
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#define NV_XTL_BASE_ADDRESS 593920

‎src/common/inc/swref/published/hopper/gh100/pri_nv_xal_ep.h

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@@ -47,5 +47,17 @@
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#define NV_XAL_EP_INTR_0_PRI_RSP_TIMEOUT 3:3
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#define NV_XAL_EP_INTR_0_PRI_RSP_TIMEOUT_PENDING 0x1
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#define NV_XAL_EP_SCPM_PRI_DUMMY_DATA_PATTERN_INIT 0xbadf0200
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#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT 0x0010f364 /* RW-4R */
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#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIUF */
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#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */
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#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIUF */
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#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */
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#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT 0x0010f37c /* RW-4R */
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#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIUF */
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#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */
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#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIUF */
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#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */
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#endif // __gh100_pri_nv_xal_ep_h__
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