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KarelPeetersKarelPeeters
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Run cargo fmt again.
1 parent b482ab4 commit 133cb7f

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16 files changed

+81
-59
lines changed

16 files changed

+81
-59
lines changed

‎rust/hwl_language/src/data/parsed.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -105,7 +105,7 @@ pub enum ModulePort<'a> {
105105
}
106106

107107
impl FileContent {
108-
pub fn items_with_ref(&self) -> impl Iterator<Item=(AstRefItem, &ast::Item)> {
108+
pub fn items_with_ref(&self) -> impl Iterator<Item = (AstRefItem, &ast::Item)> {
109109
self.items.iter().enumerate().map(move |(i, item)| {
110110
(
111111
AstRefItem {

‎rust/hwl_language/src/main.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -101,7 +101,7 @@ fn build_source_database(root: &Path) -> Result<SourceDatabase, SourceSetError>
101101

102102
Ok(())
103103
})
104-
.unwrap();
104+
.unwrap();
105105

106106
if source_database.len() == 0 {
107107
println!("Warning: no input files found");

‎rust/hwl_language/src/new/check.rs

Lines changed: 32 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -73,8 +73,14 @@ pub enum TypeContainsReason {
7373
},
7474
Operator(Span),
7575
InstanceModule(Span),
76-
InstancePortInput { span_connection_port_id: Span, span_port_ty: Span },
77-
InstancePortOutput { span_connection_signal_id: Span, span_signal_ty: Span },
76+
InstancePortInput {
77+
span_connection_port_id: Span,
78+
span_port_ty: Span,
79+
},
80+
InstancePortOutput {
81+
span_connection_signal_id: Span,
82+
span_signal_ty: Span,
83+
},
7884
}
7985

8086
impl TypeContainsReason {
@@ -87,26 +93,31 @@ impl TypeContainsReason {
8793
span_target_ty,
8894
} => diag
8995
.add_info(span_target, format!("target requires type `{}`", target_ty_str))
90-
.add_info(
91-
span_target_ty,
92-
format!("target type `{}` set here", target_ty_str),
93-
),
94-
TypeContainsReason::Operator(span) => diag.add_info(
95-
span,
96-
format!("operator requires type `{}`", target_ty_str),
97-
),
98-
TypeContainsReason::InstanceModule(span) => diag.add_info(
99-
span,
100-
format!("module instance requires `{}`", target_ty_str),
101-
),
102-
TypeContainsReason::InstancePortInput { span_connection_port_id, span_port_ty } => {
103-
diag.add_info(span_connection_port_id, format!("input port has type `{}`", target_ty_str))
104-
.add_info(span_port_ty, "port type set here")
96+
.add_info(span_target_ty, format!("target type `{}` set here", target_ty_str)),
97+
TypeContainsReason::Operator(span) => {
98+
diag.add_info(span, format!("operator requires type `{}`", target_ty_str))
10599
}
106-
TypeContainsReason::InstancePortOutput { span_connection_signal_id, span_signal_ty } => {
107-
diag.add_info(span_connection_signal_id, format!("target signal has type `{}`", target_ty_str))
108-
.add_info(span_signal_ty, "target signal type set here")
100+
TypeContainsReason::InstanceModule(span) => {
101+
diag.add_info(span, format!("module instance requires `{}`", target_ty_str))
109102
}
103+
TypeContainsReason::InstancePortInput {
104+
span_connection_port_id,
105+
span_port_ty,
106+
} => diag
107+
.add_info(
108+
span_connection_port_id,
109+
format!("input port has type `{}`", target_ty_str),
110+
)
111+
.add_info(span_port_ty, "port type set here"),
112+
TypeContainsReason::InstancePortOutput {
113+
span_connection_signal_id,
114+
span_signal_ty,
115+
} => diag
116+
.add_info(
117+
span_connection_signal_id,
118+
format!("target signal has type `{}`", target_ty_str),
119+
)
120+
.add_info(span_signal_ty, "target signal type set here"),
110121
}
111122
}
112123
}
@@ -154,10 +165,7 @@ pub fn check_type_contains_compile_value(
154165
let diag = diag
155166
.add_error(
156167
value.span,
157-
format!(
158-
"source value `{}` does not fit",
159-
value.inner.to_diagnostic_string()
160-
),
168+
format!("source value `{}` does not fit", value.inner.to_diagnostic_string()),
161169
)
162170
.finish();
163171
Err(diags.report(diag))

‎rust/hwl_language/src/new/compile.rs

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -432,7 +432,10 @@ impl CompileState<'_> {
432432
}
433433
}
434434

435-
pub fn elaborate_module(&mut self, module_elaboration: ModuleElaborationInfo) -> Result<(IrModule, Vec<Port>), ErrorGuaranteed> {
435+
pub fn elaborate_module(
436+
&mut self,
437+
module_elaboration: ModuleElaborationInfo,
438+
) -> Result<(IrModule, Vec<Port>), ErrorGuaranteed> {
436439
// check cache
437440
let cache_key = module_elaboration.to_cache_key();
438441
if let Some(result) = self.elaborated_modules_cache.get(&cache_key) {
@@ -451,7 +454,8 @@ impl CompileState<'_> {
451454
// put into cache and return
452455
// this is correct even for errors caused by cycles:
453456
// _every_ item in the cycle would always trigger the cycle, so we can mark all of them as errors
454-
self.elaborated_modules_cache.insert_first(cache_key, elaboration_result.clone());
457+
self.elaborated_modules_cache
458+
.insert_first(cache_key, elaboration_result.clone());
455459

456460
elaboration_result
457461
}

‎rust/hwl_language/src/new/expression.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,7 @@ impl CompileState<'_> {
5656
expr.span,
5757
"dummy expression used here",
5858
))
59-
},
59+
}
6060
ExpressionKind::Undefined => Ok(MaybeCompile::Compile(CompileValue::Undefined)),
6161
ExpressionKind::Type => Ok(MaybeCompile::Compile(CompileValue::Type(Type::Type))),
6262
ExpressionKind::Wrapped(inner) => Ok(self.eval_expression(scope, vars, inner)?.inner),

‎rust/hwl_language/src/new/function.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -50,8 +50,9 @@ impl CompileState<'_> {
5050
args: &Args<I, Spanned<CompileValue>>,
5151
scope_outer: Scope,
5252
span_scope_inner: Span,
53-
) -> Result<(Scope, Vec<(Identifier, CompileValue)>), ErrorGuaranteed> where
54-
for<'i> &'i I: Into<Option<&'i Identifier>>,
53+
) -> Result<(Scope, Vec<(Identifier, CompileValue)>), ErrorGuaranteed>
54+
where
55+
for<'i> &'i I: Into<Option<&'i Identifier>>,
5556
{
5657
let diags = self.diags;
5758

@@ -203,8 +204,7 @@ impl FunctionValue {
203204
// TODO cache function calls?
204205
// TODO we already do this for module elaborations, which are similar
205206
let param_key = param_values.into_iter().map(|(_, v)| v).collect_vec();
206-
let stack_entry =
207-
ElaborationStackEntry::FunctionRun(self.item, param_key);
207+
let stack_entry = ElaborationStackEntry::FunctionRun(self.item, param_key);
208208
state
209209
.check_compile_loop(stack_entry, |state| {
210210
// run the body

‎rust/hwl_language/src/new/ir.rs

Lines changed: 13 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -248,7 +248,12 @@ impl IrExpression {
248248
IrBoolBinaryOp::Or => "||",
249249
IrBoolBinaryOp::Xor => "^",
250250
};
251-
format!("({} {} {})", left.to_diagnostic_string(m), op_str, right.to_diagnostic_string(m))
251+
format!(
252+
"({} {} {})",
253+
left.to_diagnostic_string(m),
254+
op_str,
255+
right.to_diagnostic_string(m)
256+
)
252257
}
253258
IrExpression::IntBinary(op, left, right) => {
254259
let op_str = match op {
@@ -258,9 +263,14 @@ impl IrExpression {
258263
IrIntBinaryOp::Div => "/",
259264
IrIntBinaryOp::Mod => "%",
260265
};
261-
format!("({} {} {})", left.to_diagnostic_string(m), op_str, right.to_diagnostic_string(m))
266+
format!(
267+
"({} {} {})",
268+
left.to_diagnostic_string(m),
269+
op_str,
270+
right.to_diagnostic_string(m)
271+
)
262272
}
263-
273+
264274
IrExpression::ArrayLiteral(x) => {
265275
let inner = x
266276
.iter()

‎rust/hwl_language/src/new/lower_verilog.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -641,10 +641,10 @@ fn lower_block(
641641
swriteln!(f, "{indent}end");
642642
}
643643
IrStatement::If(IfStatement {
644-
initial_if,
645-
else_ifs,
646-
final_else,
647-
}) => {
644+
initial_if,
645+
else_ifs,
646+
final_else,
647+
}) => {
648648
let mut write_if = |f: &mut String, pair: &IfCondBlockPair<IrExpression, IrBlock>| {
649649
swrite!(f, "if (");
650650
lower_expression(diag, name_map, stmt.span, &pair.cond, f)?;

‎rust/hwl_language/src/new/module.rs

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,9 @@
11
use crate::data::diagnostic::{Diagnostic, DiagnosticAddable, Diagnostics, ErrorGuaranteed};
22
use crate::front::scope::{Scope, Visibility};
33
use crate::new::block::{BlockDomain, VariableValues};
4-
use crate::new::check::{check_type_contains_compile_value, check_type_contains_type, check_type_contains_value, TypeContainsReason};
4+
use crate::new::check::{
5+
check_type_contains_compile_value, check_type_contains_type, check_type_contains_value, TypeContainsReason,
6+
};
57
use crate::new::compile::{
68
CompileState, ModuleElaborationInfo, Port, PortInfo, Register, RegisterInfo, Wire, WireInfo,
79
};
@@ -15,10 +17,10 @@ use crate::new::types::{HardwareType, Type};
1517
use crate::new::value::{AssignmentTarget, CompileValue, HardwareValueResult, MaybeCompile, NamedValue};
1618
use crate::syntax::ast;
1719
use crate::syntax::ast::{
18-
Args, Block, ClockedBlock, CombinatorialBlock, DomainKind, ExpressionKind, GenericParameter,
19-
Identifier, MaybeIdentifier, ModuleInstance, ModulePortBlock, ModulePortInBlock, ModulePortItem, ModulePortSingle,
20-
ModuleStatement, ModuleStatementKind, PortConnection, PortDirection, RegDeclaration, RegOutPortMarker,
21-
Spanned, SyncDomain, WireDeclaration, WireKind,
20+
Args, Block, ClockedBlock, CombinatorialBlock, DomainKind, ExpressionKind, GenericParameter, Identifier,
21+
MaybeIdentifier, ModuleInstance, ModulePortBlock, ModulePortInBlock, ModulePortItem, ModulePortSingle,
22+
ModuleStatement, ModuleStatementKind, PortConnection, PortDirection, RegDeclaration, RegOutPortMarker, Spanned,
23+
SyncDomain, WireDeclaration, WireKind,
2224
};
2325
use crate::syntax::pos::Span;
2426
use crate::throw;
@@ -730,9 +732,7 @@ impl BodyElaborationState<'_, '_> {
730732
};
731733

732734
match &connection_expr.inner {
733-
ExpressionKind::Dummy => {
734-
IrPortConnection::Output(None)
735-
}
735+
ExpressionKind::Dummy => IrPortConnection::Output(None),
736736
ExpressionKind::Id(id) => {
737737
let named = self.state.eval_id(scope, id)?;
738738

‎rust/hwl_language/src/syntax/pos.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -293,7 +293,7 @@ impl LineOffsets {
293293
self.line_start(line_0)..self.line_end(line_0, include_terminator)
294294
}
295295

296-
pub fn split_lines(&self, span: SpanFull, include_terminator: bool) -> impl Iterator<Item=SpanFull> + '_ {
296+
pub fn split_lines(&self, span: SpanFull, include_terminator: bool) -> impl Iterator<Item = SpanFull> + '_ {
297297
assert_eq!(span.start.file, span.end.file);
298298
let file = span.start.file;
299299

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