|
| 1 | +From 7c30e23f115ae285b497ef11af0153703111dff2 Mon Sep 17 00:00:00 2001 |
| 2 | +From: Valentin Churavy <v.churavy@gmail.com> |
| 3 | +Date: Sun, 22 Dec 2019 14:25:50 -0500 |
| 4 | +Subject: [PATCH 1/2] [SelectionDAG] Copy FP flags when visiting a binary |
| 5 | + instruction. |
| 6 | + |
| 7 | +Summary: |
| 8 | +We noticed in Julia that the sequence below no longer turned into |
| 9 | +a sequence of FMA instructions in LLVM 7+, but it did in LLVM 6. |
| 10 | + |
| 11 | +``` |
| 12 | + %29 = fmul contract <4 x double> %wide.load, %wide.load16 |
| 13 | + %30 = fmul contract <4 x double> %wide.load13, %wide.load17 |
| 14 | + %31 = fmul contract <4 x double> %wide.load14, %wide.load18 |
| 15 | + %32 = fmul contract <4 x double> %wide.load15, %wide.load19 |
| 16 | + %33 = fadd fast <4 x double> %vec.phi, %29 |
| 17 | + %34 = fadd fast <4 x double> %vec.phi10, %30 |
| 18 | + %35 = fadd fast <4 x double> %vec.phi11, %31 |
| 19 | + %36 = fadd fast <4 x double> %vec.phi12, %32 |
| 20 | +``` |
| 21 | + |
| 22 | +Unlike Clang, Julia doesn't set the `unsafe-fp-math=true` function |
| 23 | +attribute, but rather emits more local instruction flags. |
| 24 | + |
| 25 | +This partially undoes https://reviews.llvm.org/D46854 and if required I can try to minimize the test further. |
| 26 | + |
| 27 | +Reviewers: spatel, mcberg2017 |
| 28 | + |
| 29 | +Reviewed By: spatel |
| 30 | + |
| 31 | +Subscribers: chriselrod, merge_guards_bot, hiraditya, llvm-commits |
| 32 | + |
| 33 | +Tags: #llvm |
| 34 | + |
| 35 | +Differential Revision: https://reviews.llvm.org/D71495 |
| 36 | +--- |
| 37 | + .../SelectionDAG/SelectionDAGBuilder.cpp | 7 +++++ |
| 38 | + llvm/test/CodeGen/X86/fmf-reduction.ll | 26 +++++++++++++++++++ |
| 39 | + 2 files changed, 33 insertions(+) |
| 40 | + create mode 100644 llvm/test/CodeGen/X86/fmf-reduction.ll |
| 41 | + |
| 42 | +diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp |
| 43 | +index bfeb3d1bc2b..e6362c19691 100644 |
| 44 | +--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp |
| 45 | ++++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp |
| 46 | +@@ -2833,6 +2833,13 @@ void SelectionDAGBuilder::visitBinary(const User &I, unsigned Opcode) { |
| 47 | + if (isVectorReductionOp(&I)) { |
| 48 | + Flags.setVectorReduction(true); |
| 49 | + LLVM_DEBUG(dbgs() << "Detected a reduction operation:" << I << "\n"); |
| 50 | ++ |
| 51 | ++ // If no flags are set we will propagate the incoming flags, if any flags |
| 52 | ++ // are set, we will intersect them with the incoming flag and so we need to |
| 53 | ++ // copy the FMF flags here. |
| 54 | ++ if (auto *FPOp = dyn_cast<FPMathOperator>(&I)) { |
| 55 | ++ Flags.copyFMF(*FPOp); |
| 56 | ++ } |
| 57 | + } |
| 58 | + |
| 59 | + SDValue Op1 = getValue(I.getOperand(0)); |
| 60 | +diff --git a/test/CodeGen/X86/fmf-reduction.ll b/test/CodeGen/X86/fmf-reduction.ll |
| 61 | +new file mode 100644 |
| 62 | +index 00000000000..1d669d2a924 |
| 63 | +--- /dev/null |
| 64 | ++++ b/test/CodeGen/X86/fmf-reduction.ll |
| 65 | +@@ -0,0 +1,26 @@ |
| 66 | ++; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| 67 | ++; RUN: llc < %s -mtriple=x86_64-- -mattr=fma | FileCheck %s |
| 68 | ++ |
| 69 | ++; Propagation of IR FMF should not drop flags when adding the DAG reduction flag. |
| 70 | ++; This should include an FMA instruction, not separate FMUL/FADD. |
| 71 | ++ |
| 72 | ++define double @julia_dotf(<4 x double> %x, <4 x double> %y, <4 x double> %z, i1 %t3) { |
| 73 | ++; CHECK-LABEL: julia_dotf: |
| 74 | ++; CHECK: # %bb.0: |
| 75 | ++; CHECK-NEXT: vfmadd213pd {{.*#+}} ymm0 = (ymm1 * ymm0) + ymm2 |
| 76 | ++; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1 |
| 77 | ++; CHECK-NEXT: vaddpd %xmm1, %xmm0, %xmm0 |
| 78 | ++; CHECK-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] |
| 79 | ++; CHECK-NEXT: vaddsd %xmm1, %xmm0, %xmm0 |
| 80 | ++; CHECK-NEXT: vzeroupper |
| 81 | ++; CHECK-NEXT: retq |
| 82 | ++ %t1 = fmul contract <4 x double> %x, %y |
| 83 | ++ %t2 = fadd fast <4 x double> %z, %t1 |
| 84 | ++ %rdx.shuf = shufflevector <4 x double> %t2, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef> |
| 85 | ++ %bin.rdx22 = fadd fast <4 x double> %t2, %rdx.shuf |
| 86 | ++ %rdx.shuf23 = shufflevector <4 x double> %bin.rdx22, <4 x double> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> |
| 87 | ++ %bin.rdx24 = fadd fast <4 x double> %bin.rdx22, %rdx.shuf23 |
| 88 | ++ %t4 = extractelement <4 x double> %bin.rdx24, i32 0 |
| 89 | ++ ret double %t4 |
| 90 | ++} |
| 91 | ++ |
| 92 | +-- |
| 93 | +2.24.1 |
| 94 | + |
0 commit comments