Add detection of ARMv8.5-MemTag based on reserved kernel bit

Author: yuyichao

src/features_aarch64.h

@@ -60,6 +60,7 @@ JL_FEATURE_DEF(bf16, 32 + 14, 110000) // HWCAP2_BF16, ARMv8.2-BF16. Required in
 // JL_FEATURE_DEF(dgh, 32 + 15, UINT32_MAX) // HWCAP2_DGH, ARMv8.0-DGH. Not implement in LLVM yet
 JL_FEATURE_DEF(rand, 32 + 16, 0) // HWCAP2_RNG, ARMv8.5-RNG
 JL_FEATURE_DEF(bti, 32 + 17, 0) // HWCAP2_BTI
+JL_FEATURE_DEF(mte, 32 + 18, 0) // HWCAP2_MTE, ARMv8.5-MemTag (reserved as of kernel 5.9-rc1)
 
 // custom bits to match llvm model
 JL_FEATURE_DEF(v8_1a, 32 * 2 + 0, 0)
@@ -74,7 +75,6 @@ JL_FEATURE_DEF(v8_6a, 32 * 2 + 5, 110000)
 //     am: ID_AA64PFR0_EL1.AMU (0b1, 0b10)
 //     specrestrict: ID_AA64PFR0_EL1.CSV2 (0b10)
 //     predres: ID_AA64PFR0_EL1.CSV3 (0b1)
-//     mte: ID_AA64PFR1_EL1.MTE (0b1, 0b10)
 //     ecv: ID_AA64MMFR0_EL1.ECV (0b1, 0b10) (LLVM 11)
 //     lor: ID_AA64MMFR1_EL1.LO (0b1)
 //     perfmon: ID_AA64DFR0_EL1.PMUVer (0b1, 0b100, 0b101, 0b110)

src/processor_arm.cpp

@@ -277,7 +277,9 @@ constexpr auto armv8_6a = armv8_5a | get_feature_masks(v8_6a, i8mm, bf16);
 //     .DIT: dit
 //     .BT: bti
 
-// ID_AA64PFR1_EL1.SSBS: ssbs
+// ID_AA64PFR1_EL1
+//     .SSBS: ssbs
+//     .MTE: mte
 
 // ID_AA64MMFR2_EL1.AT: uscat
 
@@ -1762,7 +1764,7 @@ const std::pair<std::string,std::string> &jl_get_llvm_disasm_target(void)
 #  if JL_LLVM_VERSION > 100000
                 "+tme,"
 #  endif
-                "+am,+specrestrict,+predres,+mte,+lor,+perfmon,+spe,+tracev8.4",
+                "+am,+specrestrict,+predres,+lor,+perfmon,+spe,+tracev8.4",
 #else
                 "+dotprod",
 #endif