Merge remote-tracking branch 'upstream/master'

Author: set-soft

.github/ISSUE_TEMPLATE/bug_report.yml

@@ -9,7 +9,7 @@ body:
       required: true
     - label: I have searched existing issues (including closed ones)
       required: true
-    - label: I use KiKit at least version 1.6.0 (older version are not supported)
+    - label: I use KiKit at least version 1.7.0 (older version are not supported)
       required: true
 - type: input
   attributes:

.github/workflows/test-kikit.yml

@@ -10,7 +10,7 @@ jobs:
     runs-on: ubuntu-22.04
     strategy:
       matrix:
-        kicad-version: [v7, v7-testing, v8, v8-testing]
+        kicad-version: [v7, v7-testing, v8, v8-testing, nightly]
     steps:
       - uses: actions/checkout@v4
       - uses: ./.github/actions/setup-kicad

docs/fabrication/jlcpcb.md

@@ -7,7 +7,8 @@ kikit fab jlcpcb [OPTIONS] BOARD OUTPUTDIR
 
 When you run this command, you will find file `gerbers.zip` in `OUTPUTDIR`. This
 file can be directly uploaded to JLC PCB site. KiKit automatically detects the
-number of layers.
+number of layers. If you would like to include the project name in the archive
+name, you can supply `--autoname`
 
 If you want to name your files differently, you can specify `--nametemplate`.
 This option takes a string that should contain `{}`. This string will be

docs/panelization/cli.md

@@ -206,7 +206,7 @@ are present. You can read more about multi-board project [here](../multiboard.md
 
 - `stack`: specify the number of layers of the panel. Valid options are
   `2layer`, `4layer`, `6layer` or `inehrit` (default). The use case for this
-  option is when you design a multiple boards in a single desing and you
+  option is when you design a multiple boards in a single design and you
   separate them, however, one boards is e.g., 4 layer and one 2 layer. Then you
   design both of them as 4 layer and you specify `stack: 2layer` for the 2 layer
   one when panelizing or separating.
@@ -398,7 +398,7 @@ Add a frame around the board.
 - `cuts` - one of `none`, `both`, `v`, `h` - specify whether to add cuts to the
   corners of the frame for easy removal. Default `both`.
 
-#### Tighframe
+#### Tightframe
 
 Add a frame around the board which fills the whole area of the panel - the
 boards have just a milled slot around their perimeter.
@@ -511,7 +511,7 @@ the `plugin` field.
 
 Sets page size on the resulting panel and position the panel in the page. The
 type of style dictates paper size. The default `inherit` option inherits paper
-size from the source board. This feature is not supported on KiCAD 5
+size from the source board. This feature is not supported on KiCAD 5.
 
 **Types**: `inherit`, `custom`, `A0`, `A1`, `A2`, `A3`, `A4`, `A5`, `A`, `B`,
 `C`, `D`, `E`, `USLetter`, `USLegal`, `USLedger`, `A0-portrait`, `A1-portrait`,

kikit/actionPlugins/panelize.py

@@ -52,6 +52,10 @@ def presetDifferential(source, target):
 def transplateBoard(source, target, update=lambda x: None):
     CLEAR_MSG = "Clearing the old board in UI"
     RENDER_MSG = "Rendering the new board in UI"
+
+    target.ClearProject()
+    target.DeleteAllFootprints()
+
     items = chain(
         list(target.GetDrawings()),
         list(target.GetFootprints()),
@@ -88,10 +92,6 @@ def transplateBoard(source, target, update=lambda x: None):
         update(RENDER_MSG)
         appendItem(target, x)
 
-    for n in [n for _, n in source.GetNetInfo().NetsByNetcode().items()]:
-        update(RENDER_MSG)
-        target.Add(n)
-
     update(RENDER_MSG)
     d = target.GetDesignSettings()
     d.CloneFrom(source.GetDesignSettings())

kikit/common.py

@@ -4,7 +4,7 @@
 from typing import List, Optional, Tuple, Union, Callable
 from kikit.defs import Layer
 from kikit.typing import Box
-from pcbnewTransition import pcbnew, isV7, isV8, isV9
+from pcbnewTransition import pcbnew, kicad_major
 from kikit.intervals import AxialLine
 from pcbnewTransition.pcbnew import BOX2I, VECTOR2I, EDA_ANGLE
 import os
@@ -44,7 +44,7 @@ def fitsIn(what: Union[BOX2I, VECTOR2I], where: BOX2I) -> bool:
     Return true iff 'what' (BOX2I or VECTOR2I) is fully contained in 'where'
     (BOX2I)
     """
-    if isV7() or isV8() or isV9():
+    if kicad_major() >= 7:
         assert isinstance(what, (BOX2I, VECTOR2I, pcbnew.wxPoint))
     else:
         assert isinstance(what, (BOX2I, VECTOR2I, pcbnew.wxPoint, pcbnew.EDA_RECT))