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GrarakGrarak
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9 files changed

+867
-191
lines changed

9 files changed

+867
-191
lines changed

‎macros/src/lib.rs‎

Lines changed: 248 additions & 131 deletions
Large diffs are not rendered by default.

‎src/core/graphics/gpu.rs‎

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@ use crate::logging::debug_println;
1212
use crate::settings::Arm7Emu;
1313
use bilge::prelude::*;
1414
use std::intrinsics::unlikely;
15+
use std::mem;
1516
use std::ops::{Deref, DerefMut};
1617
use std::ptr::NonNull;
1718
use std::sync::atomic::{AtomicU16, Ordering};
@@ -78,7 +79,7 @@ pub struct PowCnt1 {
7879

7980
#[bitsize(32)]
8081
#[derive(Copy, Clone, FromBits)]
81-
struct DispCapCnt {
82+
pub struct DispCapCnt {
8283
eva: u5,
8384
not_used: u3,
8485
evb: u5,
@@ -114,7 +115,7 @@ impl DerefMut for GpuRendererWrapper {
114115
pub struct Gpu {
115116
disp_stat: [DispStat; 2],
116117
pub pow_cnt1: u16,
117-
disp_cap_cnt: DispCapCnt,
118+
pub disp_cap_cnt: DispCapCnt,
118119
frame_rate_counter: FrameRateCounter,
119120
pub v_count: u16,
120121
pub gpu_2d_regs_a: Gpu2DRegisters,
@@ -165,6 +166,10 @@ impl Gpu {
165166
self.disp_stat[cpu].into()
166167
}
167168

169+
pub const fn get_disp_stat_offset(cpu: CpuType) -> usize {
170+
mem::offset_of!(Emu, gpu.disp_stat) + cpu as usize * size_of::<DispStat>()
171+
}
172+
168173
pub fn get_disp_cap_cnt(&self) -> u32 {
169174
self.disp_cap_cnt.into()
170175
}

‎src/core/graphics/gpu_2d/registers_2d.rs‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
1+
use crate::core::emu::Emu;
12
use crate::core::graphics::gpu_2d::Gpu2DEngine;
23
use crate::logging::debug_println;
34
use bilge::prelude::*;
@@ -149,6 +150,14 @@ impl Gpu2DRegisters {
149150
self.bg_cnt[bg_num].into()
150151
}
151152

153+
pub const fn get_bg_cnt_offset(engine: Gpu2DEngine, bg_num: usize) -> usize {
154+
let offset = match engine {
155+
Gpu2DEngine::A => mem::offset_of!(Emu, gpu.gpu_2d_regs_a.bg_cnt),
156+
Gpu2DEngine::B => mem::offset_of!(Emu, gpu.gpu_2d_regs_b.bg_cnt),
157+
};
158+
offset + bg_num * size_of::<BgCnt>()
159+
}
160+
152161
pub fn set_disp_cnt(&mut self, mut mask: u32, value: u32) {
153162
if self.engine == Gpu2DEngine::B {
154163
mask &= 0xC0B1FFF7;

‎src/core/memory/dma.rs‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -116,6 +116,26 @@ impl Dma {
116116
src_buf: Vec::new(),
117117
}
118118
}
119+
120+
const fn get_offset(cpu: CpuType, channel_num: usize) -> usize {
121+
mem::offset_of!(Emu, dma) + cpu as usize * size_of::<Dma>() + mem::offset_of!(Dma, channels) + channel_num * size_of::<DmaChannel>()
122+
}
123+
124+
pub const fn get_sad_offset(cpu: CpuType, channel_num: usize) -> usize {
125+
Self::get_offset(cpu, channel_num) + mem::offset_of!(DmaChannel, sad)
126+
}
127+
128+
pub const fn get_dad_offset(cpu: CpuType, channel_num: usize) -> usize {
129+
Self::get_offset(cpu, channel_num) + mem::offset_of!(DmaChannel, dad)
130+
}
131+
132+
pub const fn get_cnt_offset(cpu: CpuType, channel_num: usize) -> usize {
133+
Self::get_offset(cpu, channel_num) + mem::offset_of!(DmaChannel, cnt)
134+
}
135+
136+
pub const fn get_fill_offset(cpu: CpuType, channel_num: usize) -> usize {
137+
Self::get_offset(cpu, channel_num) + mem::offset_of!(DmaChannel, fill)
138+
}
119139
}
120140

121141
impl Emu {

‎src/core/memory/io_arm7.rs‎

Lines changed: 12 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,20 @@
1+
use std::intrinsics::breakpoint;
2+
13
use crate::core::emu::Emu;
2-
use crate::core::memory::io_arm7_lut::{IoArm7ReadLut, IoArm7ReadLutUpper, IoArm7ReadLutWifi, IoArm7WriteLut, IoArm7WriteLutWifi};
4+
use crate::core::memory::io_arm7_lut::*;
35
use crate::utils::Convert;
46

57
impl Emu {
68
pub fn io_arm7_read<T: Convert>(&mut self, addr_offset: u32) -> T {
7-
match addr_offset & 0xF00000 {
8-
0x0 if IoArm7ReadLut::is_in_range(addr_offset) => T::from(IoArm7ReadLut::read(addr_offset, size_of::<T>() as u8, self)),
9-
0x100000 if IoArm7ReadLutUpper::is_in_range(addr_offset) => T::from(IoArm7ReadLutUpper::read(addr_offset, size_of::<T>() as u8, self)),
10-
0x800000 if IoArm7ReadLutWifi::is_in_range(addr_offset) => T::from(IoArm7ReadLutWifi::read(addr_offset, size_of::<T>() as u8, self)),
11-
_ => T::from(0),
12-
}
9+
let ret = unsafe {
10+
match addr_offset & 0xF00000 {
11+
0x0 if io_arm7::is_in_range(addr_offset) => io_arm7::read(addr_offset, size_of::<T>(), self),
12+
0x100000 if io_arm7_upper::is_in_range(addr_offset) => io_arm7_upper::read(addr_offset, size_of::<T>(), self),
13+
0x800000 if io_arm7_wifi::is_in_range(addr_offset) => io_arm7_wifi::read(addr_offset, size_of::<T>(), self),
14+
_ => 0,
15+
}
16+
};
17+
T::from(ret)
1318
}
1419

1520
pub fn io_arm7_write<T: Convert>(&mut self, addr_offset: u32, value: T) {

‎src/core/memory/io_arm7_lut.rs‎

Lines changed: 23 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -2,11 +2,13 @@ use crate::core::emu::Emu;
22
use crate::core::wifi::PaketType;
33
use crate::core::CpuType::ARM7;
44
use crate::utils::Convert;
5-
use dsvita_macros::{io_read, io_write};
5+
use dsvita_macros::io_write;
66

7-
io_read!(
8-
IoArm7ReadLut,
9-
[
7+
pub mod io_arm7 {
8+
use crate::core::CpuType::ARM7;
9+
use dsvita_macros::io_read;
10+
io_read!(
11+
(io8(0x0), |emu| 0),
1012
(io16(0x4), |emu| emu.gpu.get_disp_stat(ARM7)),
1113
(io16(0x6), |emu| emu.gpu.v_count),
1214
(io32(0xB0), |emu| emu.dma_get_sad(ARM7, 0)),
@@ -68,14 +70,20 @@ io_read!(
6870
(io8(0x509), |emu| emu.spu_get_snd_cap_cnt(1)),
6971
(io32(0x510), |emu| todo!()),
7072
(io32(0x518), |emu| todo!()),
71-
]
72-
);
73+
);
74+
}
7375

74-
io_read!(IoArm7ReadLutUpper, [(io32(0x100000), |emu| emu.ipc_fifo_recv(ARM7)), (io32(0x100010), |emu| todo!())]);
76+
pub mod io_arm7_upper {
77+
use crate::core::CpuType::ARM7;
78+
use dsvita_macros::io_read;
79+
io_read!((io32(0x100000), |emu| emu.ipc_fifo_recv(ARM7)), (io32(0x100010), |emu| todo!()));
80+
}
7581

76-
io_read!(
77-
IoArm7ReadLutWifi,
78-
[
82+
pub mod io_arm7_wifi {
83+
use crate::core::wifi::PaketType;
84+
use dsvita_macros::io_read;
85+
io_read!(
86+
(io8(0x800000), |emu| 0),
7987
(io16(0x800006), |emu| emu.wifi.w_mode_wep),
8088
(io16(0x800008), |emu| emu.wifi.w_txstat_cnt),
8189
(io16(0x800010), |emu| emu.wifi.w_irf),
@@ -115,8 +123,8 @@ io_read!(
115123
(io16(0x8000B0), |emu| emu.wifi.w_txreq_read),
116124
(io16(0x8000B8), |emu| emu.wifi.w_txstat),
117125
(io16(0x8000E8), |emu| emu.wifi.w_us_countcnt),
118-
(io16(0x8000EE), |emu| emu.wifi.w_cmd_countcnt),
119126
(io16(0x8000EA), |emu| emu.wifi.w_us_comparecnt),
127+
(io16(0x8000EE), |emu| emu.wifi.w_cmd_countcnt),
120128
(io16(0x8000F0), |emu| emu.wifi_get_w_us_compare(0)),
121129
(io16(0x8000F2), |emu| emu.wifi_get_w_us_compare(1)),
122130
(io16(0x8000F4), |emu| emu.wifi_get_w_us_compare(2)),
@@ -146,12 +154,13 @@ io_read!(
146154
(io16(0x800154), |emu| emu.wifi.w_config[14]),
147155
(io16(0x80015C), |emu| emu.wifi.w_bb_read),
148156
(io16(0x800210), |emu| emu.wifi.w_tx_seqno),
149-
]
150-
);
157+
);
158+
}
151159

152160
io_write!(
153161
IoArm7WriteLut,
154162
[
163+
(io8(0x0), |mask, value, emu| {}),
155164
(io16(0x4), |mask, value, emu| emu.gpu.set_disp_stat(ARM7, mask, value)),
156165
(io32(0xB0), |mask, value, emu| emu.dma_set_sad(ARM7, 0, mask, value)),
157166
(io32(0xB4), |mask, value, emu| emu.dma_set_dad(ARM7, 0, mask, value)),
@@ -283,6 +292,7 @@ io_write!(
283292
io_write!(
284293
IoArm7WriteLutWifi,
285294
[
295+
(io16(0x800000), |mask, value, emu| {}),
286296
(io16(0x800006), |mask, value, emu| emu.wifi_set_w_mode_wep(mask, value)),
287297
(io16(0x800008), |mask, value, emu| emu.wifi_set_w_txstat_cnt(mask, value)),
288298
(io16(0x800010), |mask, value, emu| emu.wifi_set_w_irf(mask, value)),

‎src/core/memory/io_arm9.rs‎

Lines changed: 59 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,17 @@
1+
use std::intrinsics::likely;
2+
13
use crate::core::emu::Emu;
2-
use crate::core::memory::io_arm9_lut::{IoArm9ReadLut, IoArm9ReadLutUpper, IoArm9WriteLut};
4+
use crate::core::memory::io_arm9_lut::*;
35
use crate::utils::Convert;
4-
use std::intrinsics::likely;
56

67
impl Emu {
78
pub fn io_arm9_read<T: Convert>(&mut self, addr_offset: u32) -> T {
8-
match addr_offset & 0xF00000 {
9-
0x0 if IoArm9ReadLut::is_in_range(addr_offset) => T::from(IoArm9ReadLut::read(addr_offset, size_of::<T>() as u8, self)),
10-
0x100000 if IoArm9ReadLutUpper::is_in_range(addr_offset) => T::from(IoArm9ReadLutUpper::read(addr_offset, size_of::<T>() as u8, self)),
11-
_ => T::from(0),
9+
unsafe {
10+
match addr_offset & 0xF00000 {
11+
0x0 if likely(io_arm9::is_in_range(addr_offset)) => T::from(io_arm9::read(addr_offset, size_of::<T>(), self)),
12+
0x100000 if likely(io_arm9_upper::is_in_range(addr_offset)) => T::from(io_arm9_upper::read(addr_offset, size_of::<T>(), self)),
13+
_ => T::from(0),
14+
}
1215
}
1316
}
1417

@@ -23,4 +26,54 @@ impl Emu {
2326
IoArm9WriteLut::write_fixed_slice(addr_offset, slice, self);
2427
}
2528
}
29+
30+
// pub fn io_arm9_read<T: Convert>(&mut self, addr_offset: u32) -> T {
31+
// let ret = unsafe {
32+
// let shifted_addr = addr_offset >> 8;
33+
// match shifted_addr & 0xF0FF {
34+
35+
// 0x1000 if likely(io_arm9_upper::is_in_range(addr_offset)) =>io_arm9_upper::read(addr_offset, size_of::<T>(), self),
36+
// _ => 0
37+
// }
38+
// match addr_offset & 0xF0FF00 {
39+
// 0x000000 if likely(io_arm9_0::is_in_range(addr_offset)) => io_arm9_0::read(addr_offset, size_of::<T>(), self),
40+
// 0x000100 if likely(io_arm9_1::is_in_range(addr_offset)) => io_arm9_1::read(addr_offset, size_of::<T>(), self),
41+
// 0x000200 if likely(io_arm9_2::is_in_range(addr_offset)) => io_arm9_2::read(addr_offset, size_of::<T>(), self),
42+
// 0x000300 if likely(io_arm9_3::is_in_range(addr_offset)) => io_arm9_3::read(addr_offset, size_of::<T>(), self),
43+
// 0x000600 if likely(io_arm9_6::is_in_range(addr_offset)) => io_arm9_6::read(addr_offset, size_of::<T>(), self),
44+
// 0x001000 if likely(io_arm9_gpu_b::is_in_range(addr_offset)) => io_arm9_gpu_b::read(addr_offset, size_of::<T>(), self),
45+
// 0x100000 if likely(io_arm9_upper::is_in_range(addr_offset)) => io_arm9_upper::read(addr_offset, size_of::<T>(), self),
46+
// _ => 0,
47+
// }
48+
// };
49+
// T::from(ret)
50+
// }
51+
52+
// pub fn io_arm9_write<T: Convert>(&mut self, addr_offset: u32, value: T) {
53+
// match addr_offset & 0xFF00 {
54+
// 0x0000 if likely(IoArm9Write0Lut::is_in_range(addr_offset)) => IoArm9Write0Lut::write(value.into(), addr_offset, size_of::<T>() as u8, self),
55+
// 0x0100 if likely(IoArm9Write1Lut::is_in_range(addr_offset)) => IoArm9Write1Lut::write(value.into(), addr_offset, size_of::<T>() as u8, self),
56+
// 0x0200 if likely(IoArm9Write2Lut::is_in_range(addr_offset)) => IoArm9Write2Lut::write(value.into(), addr_offset, size_of::<T>() as u8, self),
57+
// 0x0300 if likely(IoArm9Write3Lut::is_in_range(addr_offset)) => IoArm9Write3Lut::write(value.into(), addr_offset, size_of::<T>() as u8, self),
58+
// 0x0400 if likely(IoArm9Write4Lut::is_in_range(addr_offset)) => IoArm9Write4Lut::write(value.into(), addr_offset, size_of::<T>() as u8, self),
59+
// 0x0500 if likely(IoArm9Write5Lut::is_in_range(addr_offset)) => IoArm9Write5Lut::write(value.into(), addr_offset, size_of::<T>() as u8, self),
60+
// 0x0600 if likely(IoArm9Write6Lut::is_in_range(addr_offset)) => IoArm9Write6Lut::write(value.into(), addr_offset, size_of::<T>() as u8, self),
61+
// 0x1000 if likely(IoArm9WriteGpuBLut::is_in_range(addr_offset)) => IoArm9WriteGpuBLut::write(value.into(), addr_offset, size_of::<T>() as u8, self),
62+
// _ => {}
63+
// }
64+
// }
65+
66+
// pub fn io_arm9_write_fixed_slice<T: Convert>(&mut self, addr_offset: u32, slice: &[T]) {
67+
// match addr_offset & 0xFF00 {
68+
// 0x0000 if likely(IoArm9Write0Lut::is_in_range(addr_offset)) => IoArm9Write0Lut::write_fixed_slice(addr_offset, slice, self),
69+
// 0x0100 if likely(IoArm9Write1Lut::is_in_range(addr_offset)) => IoArm9Write1Lut::write_fixed_slice(addr_offset, slice, self),
70+
// 0x0200 if likely(IoArm9Write2Lut::is_in_range(addr_offset)) => IoArm9Write2Lut::write_fixed_slice(addr_offset, slice, self),
71+
// 0x0300 if likely(IoArm9Write3Lut::is_in_range(addr_offset)) => IoArm9Write3Lut::write_fixed_slice(addr_offset, slice, self),
72+
// 0x0400 if likely(IoArm9Write4Lut::is_in_range(addr_offset)) => IoArm9Write4Lut::write_fixed_slice(addr_offset, slice, self),
73+
// 0x0500 if likely(IoArm9Write5Lut::is_in_range(addr_offset)) => IoArm9Write5Lut::write_fixed_slice(addr_offset, slice, self),
74+
// 0x0600 if likely(IoArm9Write6Lut::is_in_range(addr_offset)) => IoArm9Write6Lut::write_fixed_slice(addr_offset, slice, self),
75+
// 0x1000 if likely(IoArm9WriteGpuBLut::is_in_range(addr_offset)) => IoArm9WriteGpuBLut::write_fixed_slice(addr_offset, slice, self),
76+
// _ => {}
77+
// }
78+
// }
2679
}

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