Skip to content

Commit 888afe8

Browse files
GrarakGrarak
committed
Clean up and simplify
1 parent 823f445 commit 888afe8

File tree

9 files changed

+56
-145
lines changed

9 files changed

+56
-145
lines changed

‎src/core/cpu.rs‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,9 @@
11
use crate::core::cp15::Cp15;
22
use crate::core::thread_regs::ThreadRegs;
33
use crate::core::CpuType::{ARM7, ARM9};
4-
use std::ops::DerefMut;
54

65
pub struct CpuArm9 {
7-
thread_regs: Box<ThreadRegs>,
6+
thread_regs: ThreadRegs,
87
cp15: Cp15,
98
}
109

@@ -21,7 +20,7 @@ impl CpuArm9 {
2120
}
2221

2322
pub fn regs_mut(&mut self) -> &mut ThreadRegs {
24-
self.thread_regs.deref_mut()
23+
&mut self.thread_regs
2524
}
2625

2726
pub fn cp15(&self) -> &Cp15 {
@@ -34,7 +33,7 @@ impl CpuArm9 {
3433
}
3534

3635
pub struct CpuArm7 {
37-
thread_regs: Box<ThreadRegs>,
36+
thread_regs: ThreadRegs,
3837
}
3938

4039
impl CpuArm7 {
@@ -47,7 +46,7 @@ impl CpuArm7 {
4746
}
4847

4948
pub fn regs_mut(&mut self) -> &mut ThreadRegs {
50-
self.thread_regs.deref_mut()
49+
&mut self.thread_regs
5150
}
5251

5352
pub fn cp15(&self) -> &Cp15 {

‎src/core/thread_regs.rs‎

Lines changed: 3 additions & 86 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,7 @@
11
use crate::core::cpu_regs::CpuRegs;
22
use crate::core::emu::Emu;
33
use crate::core::CpuType;
4-
use crate::jit::assembler::arm::alu_assembler::AluImm;
5-
use crate::jit::assembler::arm::transfer_assembler::{LdmStm, LdrStrImm, Msr};
6-
use crate::jit::reg::{Reg, RegReserve};
7-
use crate::jit::Cond;
4+
use crate::jit::reg::Reg;
85
use crate::logging::debug_println;
96
use crate::DEBUG_LOG;
107
use bilge::prelude::*;
@@ -61,16 +58,12 @@ pub struct ThreadRegs {
6158
pub abt: OtherModeRegs,
6259
pub irq: OtherModeRegs,
6360
pub und: OtherModeRegs,
64-
pub restore_regs_opcodes: Vec<u32>,
65-
pub save_regs_opcodes: Vec<u32>,
66-
pub restore_regs_thumb_opcodes: Vec<u32>,
67-
pub save_regs_thumb_opcodes: Vec<u32>,
6861
pub cpu: CpuRegs,
6962
}
7063

7164
impl ThreadRegs {
72-
pub fn new(cpu_type: CpuType) -> Box<Self> {
73-
let mut instance = Box::new(ThreadRegs {
65+
pub fn new(cpu_type: CpuType) -> Self {
66+
ThreadRegs {
7467
gp_regs: [0u32; 13],
7568
sp: 0,
7669
lr: 0,
@@ -84,84 +77,8 @@ impl ThreadRegs {
8477
abt: OtherModeRegs::default(),
8578
irq: OtherModeRegs::default(),
8679
und: OtherModeRegs::default(),
87-
restore_regs_opcodes: Vec::new(),
88-
save_regs_opcodes: Vec::new(),
89-
restore_regs_thumb_opcodes: Vec::new(),
90-
save_regs_thumb_opcodes: Vec::new(),
9180
cpu: CpuRegs::new(cpu_type),
92-
});
93-
94-
{
95-
let gp_regs_addr = instance.gp_regs.as_ptr() as u32;
96-
let last_regs_addr = ptr::addr_of!(instance.gp_regs[instance.gp_regs.len() - 1]) as u32;
97-
let last_regs_thumb_addr = ptr::addr_of!(instance.gp_regs[7]) as u32;
98-
let sp_addr = ptr::addr_of!(instance.sp) as u32;
99-
let cpsr_addr = ptr::addr_of!(instance.cpsr) as u32;
100-
assert_eq!(sp_addr - last_regs_addr, 4);
101-
102-
{
103-
let restore_regs_opcodes = &mut instance.restore_regs_opcodes;
104-
restore_regs_opcodes.extend(AluImm::mov32(Reg::SP, gp_regs_addr));
105-
restore_regs_opcodes.extend([
106-
LdrStrImm::ldr_offset_al(Reg::R0, Reg::SP, (cpsr_addr - gp_regs_addr) as u16),
107-
Msr::cpsr_flags(Reg::R0, Cond::AL),
108-
LdmStm::pop_post_al(RegReserve::gp()),
109-
LdrStrImm::ldr_al(Reg::SP, Reg::SP),
110-
]);
111-
restore_regs_opcodes.shrink_to_fit();
112-
}
113-
114-
{
115-
let save_regs_opcodes = &mut instance.save_regs_opcodes;
116-
save_regs_opcodes.extend(AluImm::mov32(Reg::LR, sp_addr));
117-
save_regs_opcodes.push(LdmStm::push_post(RegReserve::gp() + Reg::SP, Reg::LR, Cond::AL));
118-
save_regs_opcodes.shrink_to_fit();
119-
}
120-
121-
{
122-
let restore_regs_thumb_opcodes = &mut instance.restore_regs_thumb_opcodes;
123-
restore_regs_thumb_opcodes.extend(AluImm::mov32(Reg::SP, gp_regs_addr));
124-
restore_regs_thumb_opcodes.extend([
125-
LdrStrImm::ldr_offset_al(Reg::R0, Reg::SP, (cpsr_addr - gp_regs_addr) as u16),
126-
Msr::cpsr_flags(Reg::R0, Cond::AL),
127-
LdmStm::pop_post_al(RegReserve::gp_thumb()),
128-
LdrStrImm::ldr_offset_al(Reg::SP, Reg::SP, (sp_addr - last_regs_thumb_addr - 4) as u16),
129-
]);
130-
restore_regs_thumb_opcodes.shrink_to_fit();
131-
}
132-
133-
{
134-
let save_regs_thumb_opcodes = &mut instance.save_regs_thumb_opcodes;
135-
save_regs_thumb_opcodes.extend(AluImm::mov32(Reg::LR, last_regs_thumb_addr));
136-
save_regs_thumb_opcodes.extend([
137-
LdrStrImm::str_offset_al(Reg::SP, Reg::LR, (sp_addr - last_regs_thumb_addr) as u16),
138-
LdmStm::push_post(RegReserve::gp_thumb(), Reg::LR, Cond::AL),
139-
]);
140-
save_regs_thumb_opcodes.shrink_to_fit();
141-
}
14281
}
143-
144-
instance
145-
}
146-
147-
pub fn emit_get_reg(&self, dest_reg: Reg, src_reg: Reg) -> Vec<u32> {
148-
let reg_addr = self.get_reg(src_reg) as *const _ as u32;
149-
150-
let mut opcodes = Vec::new();
151-
opcodes.extend(AluImm::mov32(dest_reg, reg_addr));
152-
opcodes.push(LdrStrImm::ldr_al(dest_reg, dest_reg));
153-
opcodes
154-
}
155-
156-
pub fn emit_set_reg(&self, dest_reg: Reg, src_reg: Reg, tmp_reg: Reg) -> Vec<u32> {
157-
debug_assert_ne!(src_reg, tmp_reg);
158-
159-
let reg_addr = self.get_reg(dest_reg) as *const _ as u32;
160-
161-
let mut opcodes = Vec::new();
162-
opcodes.extend(AluImm::mov32(tmp_reg, reg_addr));
163-
opcodes.push(LdrStrImm::str_al(src_reg, tmp_reg));
164-
opcodes
16582
}
16683

16784
pub fn get_reg_mut_ptr(&mut self) -> *mut u32 {

‎src/jit/emitter/emit.rs‎

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,9 @@
1+
use crate::core::emu::get_regs_mut;
12
use crate::core::CpuType;
23
use crate::core::CpuType::ARM7;
34
use crate::jit::assembler::block_asm::BlockAsm;
45
use crate::jit::assembler::{BlockLabel, BlockReg};
5-
use crate::jit::inst_threag_regs_handler::{register_restore_spsr, restore_thumb_after_restore_spsr, set_pc_arm_mode};
6+
use crate::jit::inst_thread_regs_handler::{register_restore_spsr, restore_thumb_after_restore_spsr, set_pc_arm_mode};
67
use crate::jit::jit_asm::{JitAsm, JitRuntimeData};
78
use crate::jit::op::Op;
89
use crate::jit::reg::Reg;
@@ -47,17 +48,17 @@ impl<'a, const CPU: CpuType> JitAsm<'a, CPU> {
4748

4849
let restore_spsr = self.jit_buf.current_inst().out_regs.is_reserved(Reg::CPSR) && op.is_arm_alu();
4950
if restore_spsr {
50-
block_asm.call(register_restore_spsr::<CPU> as *const ());
51+
block_asm.call2(register_restore_spsr as *const (), get_regs_mut!(self.emu, CPU) as *mut _ as u32, self.emu as *mut _ as u32);
5152
}
5253

5354
if CPU == ARM7 || (!op.is_single_mem_transfer() && !op.is_multiple_mem_transfer()) {
5455
if restore_spsr {
55-
block_asm.call(restore_thumb_after_restore_spsr::<CPU> as *const ());
56+
block_asm.call1(restore_thumb_after_restore_spsr as *const (), get_regs_mut!(self.emu, CPU) as *mut _ as u32);
5657
} else {
57-
block_asm.call(set_pc_arm_mode::<CPU> as *const ())
58+
block_asm.call1(set_pc_arm_mode as *const (), get_regs_mut!(self.emu, CPU) as *mut _ as u32);
5859
}
5960
} else if restore_spsr {
60-
block_asm.call(restore_thumb_after_restore_spsr::<CPU> as *const ());
61+
block_asm.call1(restore_thumb_after_restore_spsr as *const (), get_regs_mut!(self.emu, CPU) as *mut _ as u32);
6162
}
6263

6364
if (op.is_mov() && self.jit_buf.current_inst().src_regs.is_reserved(Reg::LR) && !self.jit_buf.current_inst().out_regs.is_reserved(Reg::CPSR))

‎src/jit/emitter/emit_psr.rs‎

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,9 @@
1+
use crate::core::emu::get_regs_mut;
12
use crate::core::CpuType;
23
use crate::jit::assembler::block_asm::BlockAsm;
34
use crate::jit::assembler::{BlockOperand, BlockReg};
45
use crate::jit::inst_info::Operand;
5-
use crate::jit::inst_threag_regs_handler::{register_set_cpsr_checked, register_set_spsr_checked};
6+
use crate::jit::inst_thread_regs_handler::{register_set_cpsr_checked, register_set_spsr_checked};
67
use crate::jit::jit_asm::JitAsm;
78
use crate::jit::op::Op;
89
use crate::jit::reg::Reg;
@@ -14,20 +15,22 @@ impl<const CPU: CpuType> JitAsm<'_, CPU> {
1415
let flags = (inst_info.opcode >> 16) & 0xF;
1516

1617
let func = match inst_info.op {
17-
Op::MsrRc | Op::MsrIc => register_set_cpsr_checked::<CPU> as *const (),
18-
Op::MsrRs | Op::MsrIs => register_set_spsr_checked::<CPU> as *const (),
18+
Op::MsrRc | Op::MsrIc => register_set_cpsr_checked as *const (),
19+
Op::MsrRs | Op::MsrIs => register_set_spsr_checked as *const (),
1920
_ => unreachable!(),
2021
};
2122

2223
block_asm.save_context();
23-
block_asm.call2(
24+
block_asm.call4(
2425
func,
2526
match inst_info.operands()[0] {
2627
Operand::Reg { reg, shift: None } => BlockOperand::from(reg),
2728
Operand::Imm(imm) => BlockOperand::from(imm),
2829
_ => unreachable!(),
2930
},
3031
flags,
32+
get_regs_mut!(self.emu, CPU) as *mut _ as u32,
33+
self.emu as *mut _ as u32,
3134
);
3235
block_asm.msr_cpsr(BlockReg::Fixed(Reg::R0));
3336
block_asm.restore_reg(Reg::R8);

‎src/jit/emitter/thumb/emit_thumb.rs‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,8 @@
1+
use crate::core::emu::get_regs_mut;
12
use crate::core::CpuType;
23
use crate::core::CpuType::ARM7;
34
use crate::jit::assembler::block_asm::BlockAsm;
4-
use crate::jit::inst_threag_regs_handler::set_pc_thumb_mode;
5+
use crate::jit::inst_thread_regs_handler::set_pc_thumb_mode;
56
use crate::jit::jit_asm::JitAsm;
67
use crate::jit::op::Op;
78
use crate::jit::reg::Reg;
@@ -73,7 +74,7 @@ impl<'a, const CPU: CpuType> JitAsm<'a, CPU> {
7374
block_asm.save_context();
7475

7576
if CPU == ARM7 || !op.is_multiple_mem_transfer() {
76-
block_asm.call(set_pc_thumb_mode::<CPU> as *const ());
77+
block_asm.call1(set_pc_thumb_mode as *const (), get_regs_mut!(self.emu, CPU) as *mut _ as u32);
7778
}
7879

7980
// R9 can be used as a substitution for SP for branch prediction

‎src/jit/inst_thread_regs_handler.rs‎

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,28 @@
1+
use crate::core::emu::Emu;
2+
use crate::core::thread_regs::ThreadRegs;
3+
4+
pub unsafe extern "C" fn register_set_cpsr_checked(value: u32, flags: u8, regs: *mut ThreadRegs, emu: *mut Emu) -> u32 {
5+
(*regs).set_cpsr_with_flags(value, flags, emu.as_mut_unchecked());
6+
(*regs).cpsr
7+
}
8+
9+
pub unsafe extern "C" fn register_set_spsr_checked(value: u32, flags: u8, regs: *mut ThreadRegs) -> u32 {
10+
(*regs).set_spsr_with_flags(value, flags);
11+
(*regs).cpsr
12+
}
13+
14+
pub unsafe extern "C" fn register_restore_spsr(regs: *mut ThreadRegs, emu: *mut Emu) {
15+
(*regs).restore_spsr(emu.as_mut_unchecked());
16+
}
17+
18+
pub unsafe extern "C" fn restore_thumb_after_restore_spsr(regs: *mut ThreadRegs) {
19+
(*regs).restore_thumb_mode();
20+
}
21+
22+
pub unsafe extern "C" fn set_pc_arm_mode(regs: *mut ThreadRegs) {
23+
(*regs).force_pc_arm_mode()
24+
}
25+
26+
pub unsafe extern "C" fn set_pc_thumb_mode(regs: *mut ThreadRegs) {
27+
(*regs).force_pc_thumb_mode()
28+
}

‎src/jit/inst_threag_regs_handler.rs‎

Lines changed: 0 additions & 35 deletions
This file was deleted.

‎src/jit/mod.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ mod inst_exception_handler;
1111
pub mod inst_info;
1212
mod inst_info_thumb;
1313
mod inst_mem_handler;
14-
mod inst_threag_regs_handler;
14+
mod inst_thread_regs_handler;
1515
pub mod jit_asm;
1616
pub mod jit_memory;
1717
mod jit_memory_map;

‎src/main.rs‎

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,6 @@ use crate::settings::Settings;
2626
use crate::utils::{set_thread_prio_affinity, HeapMemU32, ThreadAffinity, ThreadPriority};
2727
use std::cell::UnsafeCell;
2828
use std::cmp::min;
29-
use std::hint::assert_unchecked;
3029
use std::intrinsics::{likely, unlikely};
3130
use std::ops::{Deref, DerefMut};
3231
use std::ptr::NonNull;
@@ -183,12 +182,10 @@ pub static mut JIT_ASM_ARM9_PTR: *mut JitAsm<{ ARM9 }> = ptr::null_mut();
183182
pub static mut JIT_ASM_ARM7_PTR: *mut JitAsm<{ ARM7 }> = ptr::null_mut();
184183

185184
pub unsafe fn get_jit_asm_ptr<'a, const CPU: CpuType>() -> *mut JitAsm<'a, CPU> {
186-
let ptr = match CPU {
187-
ARM9 => JIT_ASM_ARM9_PTR as usize,
188-
ARM7 => JIT_ASM_ARM7_PTR as usize,
189-
} as *mut JitAsm<'a, CPU>;
190-
assert_unchecked(!ptr.is_null());
191-
ptr
185+
match CPU {
186+
ARM9 => JIT_ASM_ARM9_PTR as usize as *mut JitAsm<'a, CPU>,
187+
ARM7 => JIT_ASM_ARM7_PTR as usize as *mut JitAsm<'a, CPU>,
188+
}
192189
}
193190

194191
#[inline(never)]

0 commit comments

Comments
 (0)