Cover more immediate ror cases

* Generate fewer relocation insts

Author: Grarak

src/jit/assembler/block_asm.rs

@@ -1,4 +1,5 @@
 use crate::bitset::Bitset;
+use crate::jit::assembler::arm::alu_assembler::AluShiftImm;
 use crate::jit::assembler::arm::branch_assembler::B;
 use crate::jit::assembler::basic_block::BasicBlock;
 use crate::jit::assembler::block_inst::{BlockAluOp, BlockAluSetCond, BlockInst, BlockSystemRegOp, BlockTransferOp, BranchEncoding, GuestInstInfo};
@@ -214,6 +215,16 @@ impl<'a> BlockAsm<'a> {
         if op2.operand.needs_reg_for_imm(0xFF) {
             debug_assert_eq!(op2.shift, BlockShift::default());
             let imm = op2.operand.as_imm();
+
+            let msb_ones = (imm.leading_ones() + 0x1) & !0x1;
+            if msb_ones != 0 {
+                let ror_imm = (imm << msb_ones) | (imm >> (32 - msb_ones));
+                if ror_imm & !0xFF == 0 {
+                    *op2 = (ror_imm, ShiftType::Ror, msb_ones >> 1).into();
+                    return;
+                }
+            }
+
             let lsb_zeros = imm.trailing_zeros() & !0x1;
             if (imm >> lsb_zeros) & !0xFF == 0 {
                 *op2 = (imm >> lsb_zeros, ShiftType::Ror, (32 - lsb_zeros) >> 1).into();
@@ -258,30 +269,38 @@ impl<'a> BlockAsm<'a> {
     }
 
     pub fn load_u8(&mut self, op0: impl Into<BlockReg>, op1: impl Into<BlockReg>, op2: impl Into<BlockOperandShift>) {
-        self.transfer(BlockTransferOp::Read, op0, op1, op2, false, MemoryAmount::Byte)
+        self.transfer_read(op0, op1, op2, false, MemoryAmount::Byte)
     }
 
     pub fn store_u8(&mut self, op0: impl Into<BlockReg>, op1: impl Into<BlockReg>, op2: impl Into<BlockOperandShift>) {
-        self.transfer(BlockTransferOp::Write, op0, op1, op2, false, MemoryAmount::Byte)
+        self.transfer_write(op0, op1, op2, false, MemoryAmount::Byte)
     }
 
     pub fn load_u16(&mut self, op0: impl Into<BlockReg>, op1: impl Into<BlockReg>, op2: impl Into<BlockOperandShift>) {
-        self.transfer(BlockTransferOp::Read, op0, op1, op2, false, MemoryAmount::Half)
+        self.transfer_read(op0, op1, op2, false, MemoryAmount::Half)
     }
 
     pub fn store_u16(&mut self, op0: impl Into<BlockReg>, op1: impl Into<BlockReg>, op2: impl Into<BlockOperandShift>) {
-        self.transfer(BlockTransferOp::Write, op0, op1, op2, false, MemoryAmount::Half)
+        self.transfer_write(op0, op1, op2, false, MemoryAmount::Half)
     }
 
     pub fn load_u32(&mut self, op0: impl Into<BlockReg>, op1: impl Into<BlockReg>, op2: impl Into<BlockOperandShift>) {
-        self.transfer(BlockTransferOp::Read, op0, op1, op2, false, MemoryAmount::Word)
+        self.transfer_read(op0, op1, op2, false, MemoryAmount::Word)
     }
 
     pub fn store_u32(&mut self, op0: impl Into<BlockReg>, op1: impl Into<BlockReg>, op2: impl Into<BlockOperandShift>) {
-        self.transfer(BlockTransferOp::Write, op0, op1, op2, false, MemoryAmount::Word)
+        self.transfer_write(op0, op1, op2, false, MemoryAmount::Word)
+    }
+
+    pub fn transfer_read(&mut self, op0: impl Into<BlockReg>, op1: impl Into<BlockReg>, op2: impl Into<BlockOperandShift>, signed: bool, amount: MemoryAmount) {
+        self.transfer(BlockTransferOp::Read, op0, op1, op2, signed, amount)
     }
 
-    fn transfer(&mut self, op: BlockTransferOp, op0: impl Into<BlockReg>, op1: impl Into<BlockReg>, op2: impl Into<BlockOperandShift>, signed: bool, amount: MemoryAmount) {
+    pub fn transfer_write(&mut self, op0: impl Into<BlockReg>, op1: impl Into<BlockReg>, op2: impl Into<BlockOperandShift>, signed: bool, amount: MemoryAmount) {
+        self.transfer(BlockTransferOp::Write, op0, op1, op2, signed, amount)
+    }
+
+    pub fn transfer(&mut self, op: BlockTransferOp, op0: impl Into<BlockReg>, op1: impl Into<BlockReg>, op2: impl Into<BlockOperandShift>, signed: bool, amount: MemoryAmount) {
         let mut op2 = op2.into();
         if op2.operand.needs_reg_for_imm(0xFFF) {
             self.mov(self.tmp_operand_imm_reg, op2.operand);
@@ -1003,6 +1022,11 @@ impl<'a> BlockAsm<'a> {
     pub fn finalize(&mut self, jit_mem_offset: usize) -> &Vec<u32> {
         for &branch_placeholder in &self.buf.branch_placeholders {
             let encoding = BranchEncoding::from(self.buf.opcodes[branch_placeholder]);
+            if Cond::from(u8::from(encoding.cond())) == Cond::NV {
+                self.buf.opcodes[branch_placeholder] = AluShiftImm::mov_al(Reg::R0, Reg::R0);
+                continue;
+            }
+
             let diff = if encoding.is_call_common() {
                 let opcode_index = (jit_mem_offset >> 2) + branch_placeholder;
                 let branch_to = u32::from(encoding.index()) >> 2;

src/jit/assembler/block_reg_allocator.rs

@@ -1,3 +1,4 @@
+use crate::bitset::Bitset;
 use crate::jit::assembler::block_asm::BLOCK_LOG;
 use crate::jit::assembler::block_inst::{BlockAluOp, BlockAluSetCond, BlockInst, BlockInstKind, BlockTransferOp};
 use crate::jit::assembler::block_reg_set::BlockRegSet;
@@ -251,7 +252,7 @@ impl BlockRegAllocator {
         }
     }
 
-    fn relocate_guest_regs(&mut self, guest_regs: RegReserve, live_ranges: &[BlockRegSet], is_input: bool) {
+    fn relocate_guest_regs(&mut self, guest_regs: RegReserve, live_ranges: &[BlockRegSet], inputs: &BlockRegSet, used_regs: &[BlockRegSet], is_input: bool) {
         let mut relocatable_regs = RegReserve::new();
         for guest_reg in guest_regs {
             if self.stored_mapping[guest_reg as usize] != guest_reg
@@ -262,19 +263,23 @@ impl BlockRegAllocator {
             }
         }
 
+        let mut spilled_regs = Vec::new();
         for guest_reg in relocatable_regs {
             if let Some(currently_used_by) = self.stored_mapping_reverse[guest_reg as usize] {
                 self.spilled += BlockReg::Any(currently_used_by);
                 self.gen_pre_handle_spilled_inst(currently_used_by, guest_reg, BlockTransferOp::Write);
                 self.remove_stored_mapping(currently_used_by);
+                spilled_regs.push((BlockReg::Any(currently_used_by), guest_reg, self.pre_allocate_insts.len() - 1));
             }
         }
 
+        let mut dirty_regs = RegReserve::new();
         for guest_reg in relocatable_regs {
             let reg_mapped = self.stored_mapping[guest_reg as usize];
             if reg_mapped != Reg::None {
                 if is_input {
                     self.gen_pre_move_reg(guest_reg, reg_mapped);
+                    dirty_regs += guest_reg;
                 }
                 self.remove_stored_mapping(guest_reg as u16);
                 self.set_stored_mapping(guest_reg as u16, guest_reg);
@@ -287,9 +292,34 @@ impl BlockRegAllocator {
                 debug_assert!(self.spilled.contains(BlockReg::Any(guest_reg as u16)));
                 self.spilled -= BlockReg::Any(guest_reg as u16);
                 self.gen_pre_handle_spilled_inst(guest_reg as u16, guest_reg, BlockTransferOp::Read);
+                dirty_regs += guest_reg;
             }
             self.set_stored_mapping(guest_reg as u16, guest_reg);
         }
+
+        let mut new_pre_allocate_insts_filter = Bitset::<1>::new();
+        for (spilled_reg, previous_mapping, pre_allocate_index) in spilled_regs {
+            if inputs.contains(spilled_reg) && !dirty_regs.is_reserved(previous_mapping) {
+                let reg = if live_ranges.last().unwrap().contains(spilled_reg) {
+                    self.allocate_reg(spilled_reg.as_any(), live_ranges, used_regs)
+                } else {
+                    self.allocate_local(spilled_reg.as_any(), live_ranges, used_regs)
+                };
+                self.spilled -= spilled_reg;
+                self.gen_pre_move_reg(reg, previous_mapping);
+                new_pre_allocate_insts_filter += pre_allocate_index;
+            }
+        }
+
+        if !new_pre_allocate_insts_filter.is_empty() {
+            let mut new_pre_allocate_insts = Vec::new();
+            for (i, inst) in self.pre_allocate_insts.iter().enumerate() {
+                if !new_pre_allocate_insts_filter.contains(i) {
+                    new_pre_allocate_insts.push(inst.clone());
+                }
+            }
+            self.pre_allocate_insts = new_pre_allocate_insts;
+        }
     }
 
     pub fn inst_allocate(&mut self, inst: &mut BlockInst, live_ranges: &[BlockRegSet], used_regs: &[BlockRegSet]) {
@@ -308,8 +338,8 @@ impl BlockRegAllocator {
             println!("inputs: {inputs:?}, outputs: {outputs:?}");
         }
 
-        self.relocate_guest_regs(inputs.get_guests().get_gp_regs(), live_ranges, true);
-        self.relocate_guest_regs(outputs.get_guests().get_gp_regs(), live_ranges, false);
+        self.relocate_guest_regs(inputs.get_guests().get_gp_regs(), live_ranges, &inputs, used_regs, true);
+        self.relocate_guest_regs(outputs.get_guests().get_gp_regs(), live_ranges, &inputs, used_regs, false);
 
         for any_input_reg in inputs.iter_any() {
             let reg = self.get_input_reg(any_input_reg, live_ranges, used_regs);