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GrarakGrarak
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WIP
1 parent c074e59 commit 66ff70d

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8 files changed

+183
-66
lines changed

8 files changed

+183
-66
lines changed

‎src/core/graphics/gpu_mem_buf.rs‎

Lines changed: 7 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
use crate::core::memory::mem::Memory;
2+
use crate::core::memory::regions::{OAM_SIZE, STANDARD_PALETTES_SIZE};
23
use crate::core::memory::vram::{Vram, VramBanks, VramCnt};
34
use crate::core::memory::{regions, vram};
45
use crate::utils::HeapMemU8;
@@ -67,17 +68,12 @@ impl GpuMemBuf {
6768
}
6869
}
6970

70-
pub fn read_palettes_oam(&mut self, mem: &mut Memory) {
71-
if mem.palettes.dirty {
72-
mem.palettes.dirty = false;
73-
self.pal_a[1].copy_from_slice(&mem.palettes.mem[..mem.palettes.mem.len() / 2]);
74-
self.pal_b[1].copy_from_slice(&mem.palettes.mem[mem.palettes.mem.len() / 2..]);
75-
}
76-
if mem.oam.dirty {
77-
mem.oam.dirty = false;
78-
self.oam_a[1].copy_from_slice(&mem.oam.mem[..mem.oam.mem.len() / 2]);
79-
self.oam_b[1].copy_from_slice(&mem.oam.mem[mem.oam.mem.len() / 2..]);
80-
}
71+
pub fn read_palettes_oam(&mut self, palettes: &[u8; STANDARD_PALETTES_SIZE as usize], oam: &[u8; OAM_SIZE as usize]) {
72+
self.pal_a[1].copy_from_slice(&palettes[..palettes.len() / 2]);
73+
self.pal_b[1].copy_from_slice(&palettes[palettes.len() / 2..]);
74+
75+
self.oam_a[1].copy_from_slice(&oam[..oam.len() / 2]);
76+
self.oam_b[1].copy_from_slice(&oam[oam.len() / 2..]);
8177
}
8278

8379
pub fn rebuild_vram_maps(&mut self) {

‎src/core/graphics/gpu_renderer.rs‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ use crate::core::graphics::gpu_3d::registers_3d::Gpu3DRegisters;
88
use crate::core::graphics::gpu_3d::renderer_3d::Gpu3DRenderer;
99
use crate::core::graphics::gpu_mem_buf::GpuMemBuf;
1010
use crate::core::memory::mem::Memory;
11+
use crate::core::memory::regions::{OAM_SIZE, STANDARD_PALETTES_SIZE};
1112
use crate::core::memory::vram;
1213
use crate::core::memory::vram::Vram;
1314
use crate::presenter::{Presenter, PRESENTER_SCREEN_HEIGHT, PRESENTER_SCREEN_WIDTH};
@@ -129,7 +130,6 @@ impl GpuRenderer {
129130

130131
pub fn on_scanline_finish(&mut self, mem: &mut Memory, pow_cnt1: PowCnt1, registers_3d: &mut Gpu3DRegisters, breakout_imm: &mut bool) {
131132
if self.sample_2d {
132-
self.common.mem_buf.read_palettes_oam(mem);
133133
self.common.pow_cnt1[1] = pow_cnt1;
134134
self.sample_2d = false;
135135
self.ready_2d = true;
@@ -322,7 +322,7 @@ impl GpuRenderer {
322322
}
323323
}
324324

325-
pub fn read_vram(&mut self, vram: &[u8; vram::TOTAL_SIZE]) {
325+
pub fn read_vram(&mut self, palettes: &[u8; STANDARD_PALETTES_SIZE as usize], vram: &[u8; vram::TOTAL_SIZE], oam: &[u8; OAM_SIZE as usize]) {
326326
if self.quit {
327327
return;
328328
}
@@ -331,5 +331,6 @@ impl GpuRenderer {
331331
let _read_vram = self.read_vram_condvar.wait(read_vram).unwrap();
332332

333333
self.common.mem_buf.read_vram(vram);
334+
self.common.mem_buf.read_palettes_oam(palettes, oam);
334335
}
335336
}

‎src/core/memory/mem.rs‎

Lines changed: 42 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@ use crate::core::memory::mmu::{MmuArm7, MmuArm9, MMU_PAGE_SHIFT, MMU_PAGE_SIZE};
44
use crate::core::memory::oam::Oam;
55
use crate::core::memory::palettes::Palettes;
66
use crate::core::memory::regions;
7+
use crate::core::memory::regions::{OAM_SIZE, STANDARD_PALETTES_SIZE};
78
use crate::core::memory::vram::Vram;
89
use crate::core::memory::wifi::Wifi;
910
use crate::core::memory::wram::Wram;
@@ -23,9 +24,7 @@ pub struct Memory {
2324
pub shm: Shm,
2425
pub wram: Wram,
2526
pub wifi: Wifi,
26-
pub palettes: Palettes,
2727
pub vram: Vram,
28-
pub oam: Oam,
2928
pub mmu_arm9: MmuArm9,
3029
pub mmu_arm7: MmuArm7,
3130
}
@@ -246,18 +245,19 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryIo<CPU, TCM, T> {
246245
}
247246

248247
fn read_palettes(addr: u32, emu: &mut Emu) -> T {
249-
emu.mem.palettes.read(addr)
248+
unsafe { unreachable_unchecked() }
250249
}
251250

252251
fn read_vram(addr: u32, emu: &mut Emu) -> T {
253252
emu.vram_read::<CPU, _>(addr)
254253
}
255254

256255
fn read_oam(addr: u32, emu: &mut Emu) -> T {
257-
emu.mem.oam.read(addr)
256+
unsafe { unreachable_unchecked() }
258257
}
259258

260259
fn read_gba(_: u32, _: &mut Emu) -> T {
260+
println!("{CPU:?} read gba");
261261
T::from(0xFFFFFFFF)
262262
}
263263

@@ -266,6 +266,7 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryIo<CPU, TCM, T> {
266266
}
267267

268268
fn read_bios(_: u32, _: &mut Emu) -> T {
269+
println!("{CPU:?} read bios");
269270
match CPU {
270271
ARM9 => T::from(0),
271272
ARM7 => unsafe { unreachable_unchecked() },
@@ -306,18 +307,20 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryIo<CPU, TCM, T> {
306307
}
307308

308309
fn write_palettes(addr: u32, value: T, emu: &mut Emu) {
309-
emu.mem.palettes.write(addr, value);
310+
unsafe { unreachable_unchecked() }
310311
}
311312

312313
fn write_vram(addr: u32, value: T, emu: &mut Emu) {
313314
write_vram!(addr, size_of::<T>(), emu, { emu.vram_write::<CPU, _>(addr, value) });
314315
}
315316

316317
fn write_oam(addr: u32, value: T, emu: &mut Emu) {
317-
emu.mem.oam.write(addr, value);
318+
unsafe { unreachable_unchecked() }
318319
}
319320

320-
fn write_gba(_: u32, _: T, _: &mut Emu) {}
321+
fn write_gba(_: u32, _: T, _: &mut Emu) {
322+
println!("{CPU:?} write gba");
323+
}
321324
}
322325

323326
struct MemoryMultipleSliceIo<const CPU: CpuType, const TCM: bool, T: Convert> {
@@ -384,7 +387,7 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryMultipleSliceIo<CPU,
384387
}
385388

386389
fn read_palettes(addr: u32, slice: &mut [T], emu: &mut Emu) {
387-
emu.mem.palettes.read_slice(addr, slice);
390+
unsafe { unreachable_unchecked() }
388391
}
389392

390393
fn read_vram(addr: u32, slice: &mut [T], emu: &mut Emu) {
@@ -395,10 +398,11 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryMultipleSliceIo<CPU,
395398
}
396399

397400
fn read_oam(addr: u32, slice: &mut [T], emu: &mut Emu) {
398-
emu.mem.oam.read_slice(addr, slice);
401+
unsafe { unreachable_unchecked() }
399402
}
400403

401-
fn read_gba(_: u32, slice: &mut [T], _: &mut Emu) {
404+
fn read_gba(addr: u32, slice: &mut [T], _: &mut Emu) {
405+
println!("{CPU:?} read slice gba {addr:x} {TCM} {}", size_of::<T>());
402406
slice.fill(T::from(0xFFFFFFFF));
403407
}
404408

@@ -407,6 +411,7 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryMultipleSliceIo<CPU,
407411
}
408412

409413
fn read_bios(_: u32, slice: &mut [T], _: &mut Emu) {
414+
println!("{CPU:?} read slice bios");
410415
slice.fill(T::from(0));
411416
}
412417

@@ -457,7 +462,7 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryMultipleSliceIo<CPU,
457462
}
458463

459464
fn write_palettes(addr: u32, slice: &[T], emu: &mut Emu) {
460-
emu.mem.palettes.write_slice(addr, slice);
465+
unsafe { unreachable_unchecked() }
461466
}
462467

463468
fn write_vram(addr: u32, slice: &[T], emu: &mut Emu) {
@@ -466,10 +471,12 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryMultipleSliceIo<CPU,
466471
}
467472

468473
fn write_oam(addr: u32, slice: &[T], emu: &mut Emu) {
469-
emu.mem.oam.write_slice(addr, slice);
474+
unsafe { unreachable_unchecked() }
470475
}
471476

472-
fn write_gba(_: u32, _: &[T], _: &mut Emu) {}
477+
fn write_gba(_: u32, _: &[T], _: &mut Emu) {
478+
println!("{CPU:?} write slice gba");
479+
}
473480
}
474481

475482
struct MemoryFixedSliceIo<const CPU: CpuType, const TCM: bool, T: Convert> {
@@ -535,18 +542,19 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryFixedSliceIo<CPU, TC
535542
}
536543

537544
fn read_palettes(addr: u32, slice: &mut [T], emu: &mut Emu) {
538-
slice.fill(emu.mem.palettes.read(addr));
545+
unsafe { unreachable_unchecked() }
539546
}
540547

541548
fn read_vram(addr: u32, slice: &mut [T], emu: &mut Emu) {
542549
slice.fill(emu.vram_read::<CPU, _>(addr));
543550
}
544551

545552
fn read_oam(addr: u32, slice: &mut [T], emu: &mut Emu) {
546-
slice.fill(emu.mem.oam.read(addr));
553+
unsafe { unreachable_unchecked() }
547554
}
548555

549556
fn read_gba(_: u32, slice: &mut [T], _: &mut Emu) {
557+
println!("{CPU:?} read fixed gba");
550558
slice.fill(T::from(0xFFFFFFFF));
551559
}
552560

@@ -555,6 +563,7 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryFixedSliceIo<CPU, TC
555563
}
556564

557565
fn read_bios(_: u32, slice: &mut [T], _: &mut Emu) {
566+
println!("{CPU:?} read fixed bios");
558567
slice.fill(T::from(0));
559568
}
560569

@@ -600,7 +609,7 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryFixedSliceIo<CPU, TC
600609
}
601610

602611
fn write_palettes(addr: u32, slice: &[T], emu: &mut Emu) {
603-
emu.mem.palettes.write(addr, unsafe { *slice.last().unwrap_unchecked() });
612+
unsafe { unreachable_unchecked() }
604613
}
605614

606615
fn write_vram(addr: u32, slice: &[T], emu: &mut Emu) {
@@ -610,10 +619,12 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryFixedSliceIo<CPU, TC
610619
}
611620

612621
fn write_oam(addr: u32, slice: &[T], emu: &mut Emu) {
613-
emu.mem.oam.write(addr, unsafe { *slice.last().unwrap_unchecked() })
622+
unsafe { unreachable_unchecked() }
614623
}
615624

616-
fn write_gba(_: u32, _: &[T], _: &mut Emu) {}
625+
fn write_gba(_: u32, _: &[T], _: &mut Emu) {
626+
println!("{CPU:?} write gba");
627+
}
617628
}
618629

619630
struct MemoryMultipleMemsetIo<const CPU: CpuType, const TCM: bool, T: Convert> {
@@ -673,7 +684,7 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryMultipleMemsetIo<CPU
673684
}
674685

675686
fn write_palettes(addr: u32, value: T, size: usize, emu: &mut Emu) {
676-
emu.mem.palettes.write_memset(addr, value, size);
687+
todo!("{CPU:?} {addr:x} {TCM}");
677688
}
678689

679690
fn write_vram(addr: u32, value: T, size: usize, emu: &mut Emu) {
@@ -684,10 +695,12 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryMultipleMemsetIo<CPU
684695
}
685696

686697
fn write_oam(addr: u32, value: T, size: usize, emu: &mut Emu) {
687-
emu.mem.oam.write_memset(addr, value, size);
698+
unsafe { unreachable_unchecked() }
688699
}
689700

690-
fn write_gba(_: u32, _: T, _: usize, _: &mut Emu) {}
701+
fn write_gba(_: u32, _: T, _: usize, _: &mut Emu) {
702+
println!("{CPU:?} write memset gba");
703+
}
691704
}
692705

693706
impl Memory {
@@ -696,9 +709,7 @@ impl Memory {
696709
shm: Shm::new("physical", regions::TOTAL_MEM_SIZE as usize).unwrap(),
697710
wram: Wram::new(),
698711
wifi: Wifi::new(),
699-
palettes: Palettes::new(),
700712
vram: Vram::default(),
701-
oam: Oam::new(),
702713
mmu_arm9: MmuArm9::new(),
703714
mmu_arm7: MmuArm7::new(),
704715
}
@@ -708,13 +719,19 @@ impl Memory {
708719
self.shm.fill(0);
709720
self.wram = Wram::new();
710721
self.wifi = Wifi::new();
711-
self.palettes = Palettes::new();
712722
self.vram = Vram::default();
713-
self.oam = Oam::new();
714723
}
715724
}
716725

717726
impl Emu {
727+
pub fn mem_get_palettes(&self) -> &'static [u8; STANDARD_PALETTES_SIZE as usize] {
728+
unsafe { mem::transmute(self.mem.shm.as_ptr().add(regions::PALETTES_REGION.shm_offset)) }
729+
}
730+
731+
pub fn mem_get_oam(&self) -> &'static [u8; OAM_SIZE as usize] {
732+
unsafe { mem::transmute(self.mem.shm.as_ptr().add(regions::OAM_REGION.shm_offset)) }
733+
}
734+
718735
pub fn get_shm_offset<const CPU: CpuType, const TCM: bool, const WRITE: bool>(&self, addr: u32) -> usize {
719736
let mmu = {
720737
if CPU == ARM9 && TCM {

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