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GrarakGrarak
committed
Map remaining memory regions to mmu
1 parent 66ff70d commit 2efdc0c

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7 files changed

+25
-272
lines changed

7 files changed

+25
-272
lines changed

‎src/core/graphics/gpu_mem_buf.rs‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,3 @@
1-
use crate::core::memory::mem::Memory;
21
use crate::core::memory::regions::{OAM_SIZE, STANDARD_PALETTES_SIZE};
32
use crate::core::memory::vram::{Vram, VramBanks, VramCnt};
43
use crate::core::memory::{regions, vram};

‎src/core/memory/mem.rs‎

Lines changed: 18 additions & 120 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,6 @@
11
use crate::core::cp15::TcmState;
22
use crate::core::emu::Emu;
33
use crate::core::memory::mmu::{MmuArm7, MmuArm9, MMU_PAGE_SHIFT, MMU_PAGE_SIZE};
4-
use crate::core::memory::oam::Oam;
5-
use crate::core::memory::palettes::Palettes;
64
use crate::core::memory::regions;
75
use crate::core::memory::regions::{OAM_SIZE, STANDARD_PALETTES_SIZE};
86
use crate::core::memory::vram::Vram;
@@ -39,15 +37,6 @@ macro_rules! create_io_read_lut {
3937
Self::read_io_ports,
4038
Self::read_palettes,
4139
Self::read_vram,
42-
Self::read_oam,
43-
Self::read_gba,
44-
Self::read_gba,
45-
Self::read_gba,
46-
Self::read_invalid,
47-
Self::read_invalid,
48-
Self::read_invalid,
49-
Self::read_invalid,
50-
Self::read_bios,
5140
]
5241
};
5342
}
@@ -62,8 +51,6 @@ macro_rules! create_io_write_lut {
6251
Self::write_io_ports,
6352
Self::write_palettes,
6453
Self::write_vram,
65-
Self::write_oam,
66-
Self::write_gba,
6754
]
6855
};
6956
}
@@ -209,12 +196,12 @@ struct MemoryIo<const CPU: CpuType, const TCM: bool, T: Convert> {
209196
}
210197

211198
impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryIo<CPU, TCM, T> {
212-
const READ_LUT: [fn(u32, &mut Emu) -> T; 16] = create_io_read_lut!();
213-
const WRITE_LUT: [fn(u32, T, &mut Emu); 9] = create_io_write_lut!();
199+
const READ_LUT: [fn(u32, &mut Emu) -> T; 7] = create_io_read_lut!();
200+
const WRITE_LUT: [fn(u32, T, &mut Emu); 7] = create_io_write_lut!();
214201

215202
fn read(addr: u32, emu: &mut Emu) -> T {
216203
read_dtcm!(CPU, TCM, addr, emu, shm_offset, { utils::read_from_mem(&emu.mem.shm, shm_offset) });
217-
Self::READ_LUT[((addr >> 24) & 0xF) as usize](addr, emu)
204+
unsafe { Self::READ_LUT.get_unchecked(((addr >> 24) & 0xF) as usize)(addr, emu) }
218205
}
219206

220207
fn read_itcm(addr: u32, emu: &mut Emu) -> T {
@@ -244,35 +231,14 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryIo<CPU, TCM, T> {
244231
)
245232
}
246233

247-
fn read_palettes(addr: u32, emu: &mut Emu) -> T {
234+
fn read_palettes(_: u32, _: &mut Emu) -> T {
248235
unsafe { unreachable_unchecked() }
249236
}
250237

251238
fn read_vram(addr: u32, emu: &mut Emu) -> T {
252239
emu.vram_read::<CPU, _>(addr)
253240
}
254241

255-
fn read_oam(addr: u32, emu: &mut Emu) -> T {
256-
unsafe { unreachable_unchecked() }
257-
}
258-
259-
fn read_gba(_: u32, _: &mut Emu) -> T {
260-
println!("{CPU:?} read gba");
261-
T::from(0xFFFFFFFF)
262-
}
263-
264-
fn read_invalid(_: u32, _: &mut Emu) -> T {
265-
unsafe { unreachable_unchecked() }
266-
}
267-
268-
fn read_bios(_: u32, _: &mut Emu) -> T {
269-
println!("{CPU:?} read bios");
270-
match CPU {
271-
ARM9 => T::from(0),
272-
ARM7 => unsafe { unreachable_unchecked() },
273-
}
274-
}
275-
276242
fn write(addr: u32, value: T, emu: &mut Emu) {
277243
write_dtcm!(CPU, TCM, addr, emu, shm_offset, { utils::write_to_mem(&mut emu.mem.shm, shm_offset, value) });
278244
let func = unsafe { Self::WRITE_LUT.get_unchecked(((addr >> 24) & 0xF) as usize) };
@@ -306,36 +272,28 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryIo<CPU, TCM, T> {
306272
);
307273
}
308274

309-
fn write_palettes(addr: u32, value: T, emu: &mut Emu) {
275+
fn write_palettes(_: u32, _: T, _: &mut Emu) {
310276
unsafe { unreachable_unchecked() }
311277
}
312278

313279
fn write_vram(addr: u32, value: T, emu: &mut Emu) {
314280
write_vram!(addr, size_of::<T>(), emu, { emu.vram_write::<CPU, _>(addr, value) });
315281
}
316-
317-
fn write_oam(addr: u32, value: T, emu: &mut Emu) {
318-
unsafe { unreachable_unchecked() }
319-
}
320-
321-
fn write_gba(_: u32, _: T, _: &mut Emu) {
322-
println!("{CPU:?} write gba");
323-
}
324282
}
325283

326284
struct MemoryMultipleSliceIo<const CPU: CpuType, const TCM: bool, T: Convert> {
327285
_data: PhantomData<T>,
328286
}
329287

330288
impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryMultipleSliceIo<CPU, TCM, T> {
331-
const READ_LUT: [fn(u32, &mut [T], &mut Emu); 16] = create_io_read_lut!();
332-
const WRITE_LUT: [fn(u32, &[T], &mut Emu); 9] = create_io_write_lut!();
289+
const READ_LUT: [fn(u32, &mut [T], &mut Emu); 7] = create_io_read_lut!();
290+
const WRITE_LUT: [fn(u32, &[T], &mut Emu); 7] = create_io_write_lut!();
333291

334292
fn read(addr: u32, slice: &mut [T], emu: &mut Emu) {
335293
read_dtcm!(CPU, TCM, addr, emu, shm_offset, {
336294
utils::read_from_mem_slice(&emu.mem.shm, shm_offset, slice);
337295
});
338-
Self::READ_LUT[((addr >> 24) & 0xF) as usize](addr, slice, emu);
296+
unsafe { Self::READ_LUT.get_unchecked(((addr >> 24) & 0xF) as usize)(addr, slice, emu) };
339297
}
340298

341299
fn read_itcm(addr: u32, slice: &mut [T], emu: &mut Emu) {
@@ -386,7 +344,7 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryMultipleSliceIo<CPU,
386344
);
387345
}
388346

389-
fn read_palettes(addr: u32, slice: &mut [T], emu: &mut Emu) {
347+
fn read_palettes(_: u32, _: &mut [T], _: &mut Emu) {
390348
unsafe { unreachable_unchecked() }
391349
}
392350

@@ -397,24 +355,6 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryMultipleSliceIo<CPU,
397355
}
398356
}
399357

400-
fn read_oam(addr: u32, slice: &mut [T], emu: &mut Emu) {
401-
unsafe { unreachable_unchecked() }
402-
}
403-
404-
fn read_gba(addr: u32, slice: &mut [T], _: &mut Emu) {
405-
println!("{CPU:?} read slice gba {addr:x} {TCM} {}", size_of::<T>());
406-
slice.fill(T::from(0xFFFFFFFF));
407-
}
408-
409-
fn read_invalid(_: u32, _: &mut [T], _: &mut Emu) {
410-
unsafe { unreachable_unchecked() }
411-
}
412-
413-
fn read_bios(_: u32, slice: &mut [T], _: &mut Emu) {
414-
println!("{CPU:?} read slice bios");
415-
slice.fill(T::from(0));
416-
}
417-
418358
fn write(addr: u32, slice: &[T], emu: &mut Emu) {
419359
write_dtcm!(CPU, TCM, addr, emu, shm_offset, {
420360
utils::write_to_mem_slice(&mut emu.mem.shm, shm_offset as usize, slice);
@@ -461,37 +401,29 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryMultipleSliceIo<CPU,
461401
)
462402
}
463403

464-
fn write_palettes(addr: u32, slice: &[T], emu: &mut Emu) {
404+
fn write_palettes(_: u32, _: &[T], _: &mut Emu) {
465405
unsafe { unreachable_unchecked() }
466406
}
467407

468408
fn write_vram(addr: u32, slice: &[T], emu: &mut Emu) {
469409
emu.vram_write_slice::<CPU, _>(addr, slice);
470410
emu.jit.invalidate_block(addr, size_of_val(slice));
471411
}
472-
473-
fn write_oam(addr: u32, slice: &[T], emu: &mut Emu) {
474-
unsafe { unreachable_unchecked() }
475-
}
476-
477-
fn write_gba(_: u32, _: &[T], _: &mut Emu) {
478-
println!("{CPU:?} write slice gba");
479-
}
480412
}
481413

482414
struct MemoryFixedSliceIo<const CPU: CpuType, const TCM: bool, T: Convert> {
483415
_data: PhantomData<T>,
484416
}
485417

486418
impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryFixedSliceIo<CPU, TCM, T> {
487-
const READ_LUT: [fn(u32, &mut [T], &mut Emu); 16] = create_io_read_lut!();
488-
const WRITE_LUT: [fn(u32, &[T], &mut Emu); 9] = create_io_write_lut!();
419+
const READ_LUT: [fn(u32, &mut [T], &mut Emu); 7] = create_io_read_lut!();
420+
const WRITE_LUT: [fn(u32, &[T], &mut Emu); 7] = create_io_write_lut!();
489421

490422
fn read(addr: u32, slice: &mut [T], emu: &mut Emu) {
491423
read_dtcm!(CPU, TCM, addr, emu, shm_offset, {
492424
slice.fill(utils::read_from_mem(&emu.mem.shm, shm_offset));
493425
});
494-
Self::READ_LUT[((addr >> 24) & 0xF) as usize](addr, slice, emu);
426+
unsafe { Self::READ_LUT.get_unchecked(((addr >> 24) & 0xF) as usize)(addr, slice, emu) };
495427
}
496428

497429
fn read_itcm(addr: u32, slice: &mut [T], emu: &mut Emu) {
@@ -541,32 +473,14 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryFixedSliceIo<CPU, TC
541473
)
542474
}
543475

544-
fn read_palettes(addr: u32, slice: &mut [T], emu: &mut Emu) {
476+
fn read_palettes(_: u32, _: &mut [T], _: &mut Emu) {
545477
unsafe { unreachable_unchecked() }
546478
}
547479

548480
fn read_vram(addr: u32, slice: &mut [T], emu: &mut Emu) {
549481
slice.fill(emu.vram_read::<CPU, _>(addr));
550482
}
551483

552-
fn read_oam(addr: u32, slice: &mut [T], emu: &mut Emu) {
553-
unsafe { unreachable_unchecked() }
554-
}
555-
556-
fn read_gba(_: u32, slice: &mut [T], _: &mut Emu) {
557-
println!("{CPU:?} read fixed gba");
558-
slice.fill(T::from(0xFFFFFFFF));
559-
}
560-
561-
fn read_invalid(_: u32, _: &mut [T], _: &mut Emu) {
562-
unsafe { unreachable_unchecked() }
563-
}
564-
565-
fn read_bios(_: u32, slice: &mut [T], _: &mut Emu) {
566-
println!("{CPU:?} read fixed bios");
567-
slice.fill(T::from(0));
568-
}
569-
570484
fn write(addr: u32, slice: &[T], emu: &mut Emu) {
571485
write_dtcm!(CPU, TCM, addr, emu, shm_offset, {
572486
utils::write_to_mem(&mut emu.mem.shm, shm_offset, unsafe { slice.last().unwrap_unchecked() })
@@ -608,7 +522,7 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryFixedSliceIo<CPU, TC
608522
);
609523
}
610524

611-
fn write_palettes(addr: u32, slice: &[T], emu: &mut Emu) {
525+
fn write_palettes(_: u32, _: &[T], _: &mut Emu) {
612526
unsafe { unreachable_unchecked() }
613527
}
614528

@@ -617,22 +531,14 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryFixedSliceIo<CPU, TC
617531
emu.vram_write::<CPU, _>(addr, slice[i]);
618532
}
619533
}
620-
621-
fn write_oam(addr: u32, slice: &[T], emu: &mut Emu) {
622-
unsafe { unreachable_unchecked() }
623-
}
624-
625-
fn write_gba(_: u32, _: &[T], _: &mut Emu) {
626-
println!("{CPU:?} write gba");
627-
}
628534
}
629535

630536
struct MemoryMultipleMemsetIo<const CPU: CpuType, const TCM: bool, T: Convert> {
631537
_data: PhantomData<T>,
632538
}
633539

634540
impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryMultipleMemsetIo<CPU, TCM, T> {
635-
const WRITE_LUT: [fn(u32, T, usize, &mut Emu); 9] = create_io_write_lut!();
541+
const WRITE_LUT: [fn(u32, T, usize, &mut Emu); 7] = create_io_write_lut!();
636542

637543
fn write(addr: u32, value: T, size: usize, emu: &mut Emu) {
638544
write_dtcm!(CPU, TCM, addr, emu, shm_offset, {
@@ -683,8 +589,8 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryMultipleMemsetIo<CPU
683589
)
684590
}
685591

686-
fn write_palettes(addr: u32, value: T, size: usize, emu: &mut Emu) {
687-
todo!("{CPU:?} {addr:x} {TCM}");
592+
fn write_palettes(_: u32, _: T, _: usize, _: &mut Emu) {
593+
unsafe { unreachable_unchecked() }
688594
}
689595

690596
fn write_vram(addr: u32, value: T, size: usize, emu: &mut Emu) {
@@ -693,14 +599,6 @@ impl<const CPU: CpuType, const TCM: bool, T: Convert> MemoryMultipleMemsetIo<CPU
693599
emu.vram_write::<CPU, _>(addr + (i << write_shift) as u32, value);
694600
}
695601
}
696-
697-
fn write_oam(addr: u32, value: T, size: usize, emu: &mut Emu) {
698-
unsafe { unreachable_unchecked() }
699-
}
700-
701-
fn write_gba(_: u32, _: T, _: usize, _: &mut Emu) {
702-
println!("{CPU:?} write memset gba");
703-
}
704602
}
705603

706604
impl Memory {

‎src/core/memory/mmu.rs‎

Lines changed: 5 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,7 @@ use crate::core::cp15::TcmState;
22
use crate::core::emu::Emu;
33
use crate::core::memory::regions;
44
use crate::core::memory::regions::{
5-
ARM7_BIOS_REGION, ARM9_BIOS_REGION, DTCM_REGION, GBA_RAM_REGION, GBA_ROM_REGION, GBA_ROM_SIZE, ITCM_REGION, OAM_OFFSET, OAM_REGION, PALETTES_REGION, STANDARD_PALETTES_OFFSET, VRAM_OFFSET,
6-
V_MEM_ARM7_RANGE,
5+
ARM7_BIOS_REGION, ARM9_BIOS_REGION, DTCM_REGION, GBA_ROM_REGION, ITCM_REGION, OAM_OFFSET, OAM_REGION, PALETTES_REGION, STANDARD_PALETTES_OFFSET, VRAM_OFFSET, V_MEM_ARM7_RANGE,
76
};
87
use crate::core::CpuType;
98
use crate::core::CpuType::{ARM7, ARM9};
@@ -152,38 +151,6 @@ impl Emu {
152151
self.mem.mmu_arm9.vmem_tcm.create_map(shm, 0, addr as usize, MMU_PAGE_SIZE, false, false, false).unwrap();
153152
}
154153
}
155-
// GBA_ROM_OFFSET | GBA_ROM_OFFSET2 | GBA_RAM_OFFSET => {
156-
// *mmu_read = GBA_ROM_REGION.shm_offset;
157-
// self.mem
158-
// .mmu_arm9
159-
// .vmem_tcm
160-
// .create_page_map(
161-
// shm,
162-
// GBA_ROM_REGION.shm_offset,
163-
// base_addr as usize,
164-
// GBA_ROM_REGION.size,
165-
// addr as usize,
166-
// MMU_PAGE_SIZE,
167-
// GBA_ROM_REGION.allow_write,
168-
// )
169-
// .unwrap();
170-
// }
171-
// 0x0F000000 => {
172-
// *mmu_read = ARM9_BIOS_REGION.shm_offset;
173-
// self.mem
174-
// .mmu_arm9
175-
// .vmem_tcm
176-
// .create_page_map(
177-
// shm,
178-
// ARM9_BIOS_REGION.shm_offset,
179-
// base_addr as usize,
180-
// ARM9_BIOS_REGION.size,
181-
// addr as usize,
182-
// MMU_PAGE_SIZE,
183-
// ARM9_BIOS_REGION.allow_write,
184-
// )
185-
// .unwrap();
186-
// }
187154
_ => {}
188155
}
189156

@@ -232,16 +199,16 @@ impl Emu {
232199
*mmu_read_tcm = PALETTES_REGION.shm_offset;
233200
*mmu_write_tcm = PALETTES_REGION.shm_offset;
234201

235-
// self.mem.mmu_arm9.vmem_tcm.destroy_region_map(&PALETTES_REGION);
236-
// self.mem.mmu_arm9.vmem_tcm.create_region_map(&self.mem.shm, &PALETTES_REGION).unwrap();
202+
self.mem.mmu_arm9.vmem_tcm.destroy_region_map(&PALETTES_REGION);
203+
self.mem.mmu_arm9.vmem_tcm.create_region_map(&self.mem.shm, &PALETTES_REGION).unwrap();
237204

238205
let mmu_read_tcm = &mut self.mem.mmu_arm9.mmu_read_tcm[(OAM_OFFSET as usize) >> MMU_PAGE_SHIFT];
239206
let mmu_write_tcm = &mut self.mem.mmu_arm9.mmu_write_tcm[(OAM_OFFSET as usize) >> MMU_PAGE_SHIFT];
240207
*mmu_read_tcm = OAM_REGION.shm_offset;
241208
*mmu_write_tcm = OAM_REGION.shm_offset;
242209

243-
// self.mem.mmu_arm9.vmem_tcm.destroy_region_map(&OAM_REGION);
244-
// self.mem.mmu_arm9.vmem_tcm.create_region_map(&self.mem.shm, &OAM_REGION).unwrap();
210+
self.mem.mmu_arm9.vmem_tcm.destroy_region_map(&OAM_REGION);
211+
self.mem.mmu_arm9.vmem_tcm.create_region_map(&self.mem.shm, &OAM_REGION).unwrap();
245212

246213
for addr in (GBA_ROM_OFFSET..V_MEM_ARM9_RANGE).step_by(MMU_PAGE_SIZE) {
247214
let mmu_read = &mut self.mem.mmu_arm9.mmu_read_tcm[(addr as usize) >> MMU_PAGE_SHIFT];

‎src/core/memory/mod.rs‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,6 @@ mod io_arm9_lut;
77
pub mod mem;
88
pub mod mmu;
99
pub mod oam;
10-
pub mod palettes;
1110
pub mod regions;
1211
pub mod vram;
1312
mod wifi;

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