Preliminary add of fdcan source files.

Adding source files to the fdcan branch based on identical register set. These files should mostly just work.

Removed references to FDCAN3. H5 only has 2 FDCAN interfaces.

Add basic FDCAN Kconfig

FDCAN Kconfig options

Added various options for FDCAN mode, FDCAN bitrate, clock selection and division, and timing.

Added bit timing config options (nominal and data). Added stm32h56xxx pin mappings.

Fixed Data Bit Timing. Pulled in STM32H5_FDCAN_PDIV_VALUE. Added stm32_fdcan.c to Make.defs. Added DBITRATE to Kconfig

Clock source changes to FDCAN

Moved the setting of the clock source to the stm32h5xx_rcc.c file. Added notes to stm32_fdcan.c that STM32_FDCAN_FREQUENCY and STM32_FDCAN_PDIV should be set in board.h

Change STM32H5_FDCAN_PDIV to STM32_FDCAN_PDIV

Updated Kconfig to match G4 implementation. Removed stm32_fdcan_sock for now.

Removed FDCAN3 from stm32_fdcan.h

incomplete changes for bit timning

Set NBRP and DBRP registers based on STM32H7 FDCAN socket algorithm.

Added board file for initializing 1 can device. Will update later to initialize second device.

Fixed ifdefs. Changed STM32 to STM32H5.

Add some can testing changes.

Added option to configure bit timing, with automatic bit timing set as default.

Style fixes

Fixed FDCAN2 and memory access issues

FDCAN2 msgram offset was wrong by 1 word (4 bytes). I removed the + 4 at the end of the definition. This fixed the issues with fdcan2. Also changed ifdefs when setting ESI, FDF, and BRS bits. When CAN FD was used, this resulted in the first command after the endif (the setting of dest at line 2325) being skipped because it was included in the else block when it shouldn't have. This resulted in exceptions. Adjust ifdefs fixes this problem. Other minor fixes.

Restoring board files to upstream versions. These files will be pulled in later in a separate pull request. stm32h5_fdcan_test branch created for this.

Fixed Queue Mode Transmit

The can driver checks the TFFL bits in the TXFQS register. In Queue mode, this always returns 0. As a result, fdcan_txempty was always returning false, which resulted in no transmissions. This code fixes that.

Add stm32h5 fdcan chardriver to Make.defs

Author: kywwilson11

arch/arm/src/stm32h5/Kconfig

@@ -35,6 +35,8 @@ config STM32H5_STM32H5XXXX
 config STM32H5_STM32H56XXX
 	bool
 	default n
+	select STM32H5_HAVE_FDCAN1
+	select STM32H5_HAVE_FDCAN2
 	select STM32H5_HAVE_LPUART1
 	select STM32H5_HAVE_USART1
 	select STM32H5_HAVE_USART2
@@ -210,6 +212,14 @@ config STM32H5_HAVE_PHY_POLLED
 	bool
 	default n
 
+config STM32H5_HAVE_FDCAN1
+	bool
+	default n
+
+config STM32H5_HAVE_FDCAN2
+	bool
+	default n
+
 config STM32H5_HAVE_LPUART1
 	bool
 	default n
@@ -1322,6 +1332,292 @@ config STM32H5_NO_PHY
 
 endmenu # Ethernet MAC Configuration
 
+menu "FDCAN driver configuration"
+	depends on STM32H5_FDCAN
+
+choice
+	prompt "FDCAN character driver or SocketCAN support"
+	default STM32H5_FDCAN_CHARDRIVER
+
+config STM32H5_FDCAN_CHARDRIVER
+	bool "STM32 FDCAN character driver support"
+	select ARCH_HAVE_CAN_ERRORS
+	select CAN
+
+config STM32H5_FDCAN_SOCKET
+	bool "STM32 FDCAN SocketCAN support"
+	select NET_CAN_HAVE_ERRORS
+	select NET_CAN_HAVE_CANFD
+
+endchoice # FDCAN character driver or SocketCAN support
+
+config STM32H5_FDCAN_REGDEBUG
+	bool "CAN Register level debug"
+	depends on DEBUG_CAN_INFO
+	default n
+	---help---
+		Output detailed register-level CAN device debug information.
+		Requires also CONFIG_DEBUG_CAN_INFO.
+
+config STM32H5_FDCAN_QUEUE_MODE
+	bool "FDCAN QUEUE mode (vs FIFO mode)"
+	default n
+
+menu "FDCAN1 device driver options"
+	depends on STM32H5_FDCAN1
+
+choice
+	prompt "FDCAN1 frame format"
+	default STM32H5_FDCAN1_ISO11898_1
+
+config STM32H5_FDCAN1_ISO11898_1
+	bool "ISO11898-1"
+	---help---
+		Enable ISO11898-1 frame format
+
+config STM32H5_FDCAN1_NONISO_FORMAT
+	bool "Non ISO"
+	---help---
+		Enable Non ISO, Bosch CAN FD Specification V1.0
+
+endchoice # FDCAN1 frame format
+
+choice
+	prompt "FDCAN1 mode"
+	default STM32H5_FDCAN1_CLASSIC
+
+config STM32H5_FDCAN1_CLASSIC
+	bool "Classic CAN"
+	---help---
+		Enable Clasic CAN mode
+
+config STM32H5_FDCAN1_FD
+	bool "CAN FD"
+	depends on CAN_FD || NET_CAN_CANFD
+	---help---
+		Enable CAN FD mode
+
+config STM32H5_FDCAN1_FD_BRS
+	bool "CAN FD with fast bit rate switching"
+	depends on CAN_FD || NET_CAN_CANFD
+	---help---
+		Enable CAN FD mode with fast bit rate switching mode.
+
+endchoice # FDCAN1 mode
+
+menu "FDCAN1 Bit Timing"
+
+config STM32H5_FDCAN1_AUTO_BIT_TIMING
+        bool "FDCAN1 Automatic Bit Timing"
+        default y
+	---help---
+		Automatically determine FDCAN1 bit timing (nominal and data) based on bitrate.
+
+comment "Nominal Bit Timing"
+
+config STM32H5_FDCAN1_BITRATE
+	int "FDCAN bitrate"
+	default 500000
+	range 0 1000000
+	---help---
+		FDCAN1 bitrate in bits per second.  Required if STM32H5_FDCAN1 is defined.
+
+config STM32H5_FDCAN1_NTSEG1
+	int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)"
+	default 6
+	range 1 256
+        depends on !STM32H5_FDCAN1_AUTO_BIT_TIMING
+	---help---
+		The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
+
+config STM32H5_FDCAN1_NTSEG2
+	int "FDCAN1 NTSEG2 (PhaseSeg2)"
+	default 7
+	range 1 128
+        depends on !STM32H5_FDCAN1_AUTO_BIT_TIMING
+	---help---
+		The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
+
+config STM32H5_FDCAN1_NSJW
+	int "FDCAN1 synchronization jump width"
+	default 1
+	range 1 128
+        depends on !STM32H5_FDCAN1_AUTO_BIT_TIMING
+	---help---
+		The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
+
+comment "Data Bit Timing"
+	depends on CAN_FD && STM32H5_FDCAN1_FD_BRS
+
+config STM32H5_FDCAN1_DBITRATE
+	int "FDCAN1 data bitrate"
+	default 2000000
+	depends on CAN_FD && STM32H5_FDCAN1_FD_BRS
+	---help---
+		FDCAN1 bitrate in bits per second.  Required if operating in FD mode with bit rate switching (BRS).
+
+config STM32H5_FDCAN1_DTSEG1
+	int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)"
+	default 4
+	range 1 31
+	depends on CAN_FD && STM32H5_FDCAN1_FD_BRS && !STM32H5_FDCAN1_AUTO_BIT_TIMING
+	---help---
+		The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
+
+config STM32H5_FDCAN1_DTSEG2
+	int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)"
+	default 4
+	range 1 15
+	depends on CAN_FD && STM32H5_FDCAN1_FD_BRS && !STM32H5_FDCAN1_AUTO_BIT_TIMING
+	---help---
+		The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
+
+config STM32H5_FDCAN1_DSJW
+	int "FDCAN1 fast synchronization jump width"
+	default 2
+	range 1 15
+	depends on CAN_FD && STM32H5_FDCAN1_FD_BRS && !STM32H5_FDCAN1_AUTO_BIT_TIMING
+	---help---
+		The duration of a synchronization jump is Tcan_clk x DSJW.
+
+endmenu # FDCAN1 Bit Timing
+
+config STM32H5_FDCAN1_LOOPBACK
+	bool "Enable FDCAN1 loopback mode"
+	default n
+	---help---
+		Enable the FDCAN1 local loopback mode for testing purposes.
+
+endmenu # FDCAN1 device driver options
+
+menu "FDCAN2 device driver options"
+	depends on STM32H5_FDCAN2
+
+choice
+	prompt "FDCAN2 frame format"
+	default STM32H5_FDCAN2_ISO11898_1
+
+config STM32H5_FDCAN2_ISO11898_1
+	bool "ISO11898-1"
+	---help---
+		Enable ISO11898-1 frame format
+
+config STM32H5_FDCAN2_NONISO_FORMAT
+	bool "Non ISO"
+	---help---
+		Enable Non ISO, Bosch CAN FD Specification V1.0
+
+endchoice # FDCAN2 frame format
+
+choice
+	prompt "FDCAN2 mode"
+	default STM32H5_FDCAN2_CLASSIC
+
+config STM32H5_FDCAN2_CLASSIC
+	bool "Classic CAN"
+	---help---
+		Enable Clasic CAN mode
+
+config STM32H5_FDCAN2_FD
+	bool "CAN FD"
+	depends on CAN_FD || NET_CAN_CANFD
+	---help---
+		Enable CAN FD mode
+
+config STM32H5_FDCAN2_FD_BRS
+	bool "CAN FD with fast bit rate switching"
+	depends on CAN_FD || NET_CAN_CANFD
+	---help---
+		Enable CAN FD mode with fast bit rate switching mode.
+
+endchoice # FDCAN2 mode
+
+menu "FDCAN2 Bit Timing"
+
+config STM32H5_FDCAN2_AUTO_BIT_TIMING
+        bool "FDCAN2 Automatic Bit Timing"
+        default y
+	---help---
+		Automatically determine FDCAN2 bit timing (nominal and data) based on bitrate.
+
+comment "Nominal Bit Timing"
+
+config STM32H5_FDCAN2_BITRATE
+	int "FDCAN bitrate"
+	default 500000
+	range 0 1000000
+	---help---
+		FDCAN2 bitrate in bits per second.  Required if STM32H5_FDCAN2 is defined.
+
+config STM32H5_FDCAN2_NTSEG1
+	int "FDCAN2 NTSEG1 (PropSeg + PhaseSeg1)"
+	default 6
+	range 1 256
+        depends on !STM32H5_FDCAN2_AUTO_BIT_TIMING
+	---help---
+		The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
+
+config STM32H5_FDCAN2_NTSEG2
+	int "FDCAN2 NTSEG2 (PhaseSeg2)"
+	default 7
+	range 1 128
+        depends on !STM32H5_FDCAN2_AUTO_BIT_TIMING
+	---help---
+		The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
+
+config STM32H5_FDCAN2_NSJW
+	int "FDCAN2 synchronization jump width"
+	default 1
+	range 1 128
+        depends on !STM32H5_FDCAN2_AUTO_BIT_TIMING
+	---help---
+		The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
+
+comment "Data Bit Timing"
+	depends on CAN_FD && STM32H5_FDCAN2_FD_BRS
+
+config STM32H5_FDCAN2_DBITRATE
+	int "FDCAN2 data bitrate"
+	default 2000000
+	depends on CAN_FD && STM32H5_FDCAN2_FD_BRS
+	---help---
+		FDCAN2 bitrate in bits per second.  Required if operating in FD mode with bit rate switching (BRS).
+
+config STM32H5_FDCAN2_DTSEG1
+	int "FDCAN2 DTSEG1 (PropSeg + PhaseSeg1 of data phase)"
+	default 4
+	range 1 31
+	depends on CAN_FD && STM32H5_FDCAN2_FD_BRS && !STM32H5_FDCAN2_AUTO_BIT_TIMING
+	---help---
+		The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
+
+config STM32H5_FDCAN2_DTSEG2
+	int "FDCAN2 DTSEG2 (PhaseSeg2 of data phase)"
+	default 4
+	range 1 15
+	depends on CAN_FD && STM32H5_FDCAN2_FD_BRS && !STM32H5_FDCAN2_AUTO_BIT_TIMING
+	---help---
+		The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
+
+config STM32H5_FDCAN2_DSJW
+	int "FDCAN2 fast synchronization jump width"
+	default 2
+	range 1 15
+	depends on CAN_FD && STM32H5_FDCAN2_FD_BRS && !STM32H5_FDCAN2_AUTO_BIT_TIMING
+	---help---
+		The duration of a synchronization jump is Tcan_clk x DSJW.
+
+endmenu # FDCAN2 Bit Timing
+
+config STM32H5_FDCAN2_LOOPBACK
+	bool "Enable FDCAN2 loopback mode"
+	default n
+	---help---
+		Enable the FDCAN2 local loopback mode for testing purposes.
+
+endmenu # FDCAN2 device driver options
+
+endmenu # "FDCAN driver configuration"
 
 menu "I2C Configuration"
 	depends on STM32H5_I2C

arch/arm/src/stm32h5/Make.defs

@@ -54,6 +54,10 @@ ifeq ($(CONFIG_ADC),y)
 CHIP_CSRCS += stm32_adc.c
 endif
 
+ifeq ($(STM32H5_FDCAN_CHARDRIVER),y)
+CHIP_CSRCS += stm32_fdcan.c
+endif
+
 ifeq ($(CONFIG_STM32H5_SPI),y)
 CHIP_CSRCS += stm32_spi.c
 endif

arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h

@@ -98,6 +98,32 @@
 #define GPIO_ETH_RMII_TXD1_2    (GPIO_ALT|GPIO_AF11|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN12)
 #define GPIO_ETH_RMII_TXD1_3    (GPIO_ALT|GPIO_AF11|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14)
 
+/* FDCAN */
+
+#define GPIO_FDCAN1_RX_1               (GPIO_ALT | GPIO_AF9 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN11)
+#define GPIO_FDCAN1_RX_2               (GPIO_ALT | GPIO_AF9 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN8)
+#define GPIO_FDCAN1_RX_3               (GPIO_ALT | GPIO_AF9 | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN0)
+#define GPIO_FDCAN1_RX_4               (GPIO_ALT | GPIO_AF9 | GPIO_PUSHPULL | GPIO_PORTE | GPIO_PIN0)
+#define GPIO_FDCAN1_RX_5               (GPIO_ALT | GPIO_AF9 | GPIO_PUSHPULL | GPIO_PORTH | GPIO_PIN14)
+#define GPIO_FDCAN1_RX_6               (GPIO_ALT | GPIO_AF9 | GPIO_PUSHPULL | GPIO_PORTI | GPIO_PIN9)
+#define GPIO_FDCAN1_RX_7               (GPIO_ALT | GPIO_AF9 | GPIO_PUSHPULL | GPIO_PORTI | GPIO_PIN10)
+
+#define GPIO_FDCAN1_TX_1               (GPIO_ALT | GPIO_AF9 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN12)
+#define GPIO_FDCAN1_TX_2               (GPIO_ALT | GPIO_AF9 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN9)
+#define GPIO_FDCAN1_TX_3               (GPIO_ALT | GPIO_AF9 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN7)
+#define GPIO_FDCAN1_TX_4               (GPIO_ALT | GPIO_AF9 | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN1)
+#define GPIO_FDCAN1_TX_5               (GPIO_ALT | GPIO_AF9 | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN5)
+#define GPIO_FDCAN1_TX_6               (GPIO_ALT | GPIO_AF9 | GPIO_PUSHPULL | GPIO_PORTE | GPIO_PIN1)
+#define GPIO_FDCAN1_TX_7               (GPIO_ALT | GPIO_AF9 | GPIO_PUSHPULL | GPIO_PORTH | GPIO_PIN13)
+
+#define GPIO_FDCAN2_RX_1               (GPIO_ALT | GPIO_AF9 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN5)
+#define GPIO_FDCAN2_RX_2               (GPIO_ALT | GPIO_AF9 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN12)
+#define GPIO_FDCAN2_RX_3               (GPIO_ALT | GPIO_AF9 | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN9)
+
+#define GPIO_FDCAN2_TX_1               (GPIO_ALT | GPIO_AF9 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN6)
+#define GPIO_FDCAN2_TX_2               (GPIO_ALT | GPIO_AF9 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN13)
+#define GPIO_FDCAN2_TX_3               (GPIO_ALT | GPIO_AF9 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN10)
+
 /* Clocks outputs */
 
 #define GPIO_MCO_0             (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN8)