[Question] FPGA I/O assignment in subblock

[jdeitmerg]

Hi,

I've started programming a TinyFPGA BX board using Icestudio and it's been a breeze so far. Thanks for the excellent work on this project!

As my projects grew in complexity, I realized FPGA pins can only be assigned in the top level design, not in subblocks. I would like to hide some I/O complexity, which doesn't work if all physical I/O signals have to be routed down and up the design hierarchy. Take for example a simple 595 shift register that is connected to the FPGA: In the top-level design, I'd like to have 8 outputs (and a clk) and nothing else. The actual serialization and I/O access should happen in a subblock. This approach makes the design functionality-centric instead of FPGA-centric.

Is there a way to assign FPGA pins in subblocks that's not documented? Are there workarounds to make this happen?

[cavearr]

Hi @jdeitmerg! for the moment the icestudio software architectura not permit to assign I/O into submodules, onlyt at toplevel.

We are working on redefining icestudio to do it better and better and all of your commets are welcome!

I'm assign this issue to enhancement label for next versions!

[cavearr]

Hello! I am reorganizing the issues, trying to give more visibility and be able to better organize and prioritize the work and my roadmap (I will publish it very soon), I am converting some issues that are new feature requests as ideas on Github discussions.

Thanks for understanding.