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Data structure development
This page is intended to collect ideas and discussion points for the forthcoming development work on NEURON and CoreNEURON data structures, particularly in relation to host/device memory transfers and general memory management.
The existing code managing data transfer to/from an accelerator/GPU is rather explicit and error prone, with a lot of hand-written code to ensure -- for example -- that structs containing pointers have those pointers updated to be valid on the device side too, and so on. Deallocation/cleanup is also managed by hand, and was only added rather recently in some cases. We would, therefore, like to improve in these areas as part of a re-write. For example:
- Automatic lifetime management
- Abstracting away the 2-part copy-data-and-then-manually-update-pointers-to-it pattern
- ...
Re-working this area of [Core]NEURON is also an opportunity to add support for new features and optimisations. Here is a list of possible improvements, please add to it as appropriate!
- Support for placing data in different types of device/GPU memory (e.g. constants)
- Reducing device/GPU memory requirements by copying more selectively
- Finer grained control over NUMA domains / locality
- Support for GPU programming models other than OpenACC
- Support for multiple GPUs per process
- ...
- CoreNEURON data structure redesign (restricted)
- CoreNEURON data structures (restricted, slides)