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Merge pull request JuliaLang#35422 from JuliaLang/vc/llvm10_ppc
add LLVM 10 patch for ppc
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‎deps/llvm.mk

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Original file line numberDiff line numberDiff line change
@@ -425,6 +425,8 @@ $(eval $(call LLVM_PATCH,llvm-exegesis-mingw)) # mingw build
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$(eval $(call LLVM_PATCH,llvm-test-plugin-mingw)) # mingw build
426426
$(eval $(call LLVM_PATCH,llvm7-revert-D44485))
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$(eval $(call LLVM_PATCH,llvm-D75072-SCEV-add-type))
428+
$(eval $(call LLVM_PATCH,llvm-10.0-PPC_SELECT_CC)) # delete for LLVM 11
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$(eval $(call LLVM_PATCH,llvm-10.0-PPC-LI-Elimination)) # delete for LLVM 11
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endif # LLVM_VER 10.0
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# Add a JL prefix to the version map. DO NOT REMOVE

‎deps/patches/llvm-10.0-PPC-LI-Elimination.patch

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@@ -0,0 +1,161 @@
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From 5423496713e84dea2650e1703821de620f934573 Mon Sep 17 00:00:00 2001
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From: Nemanja Ivanovic <nemanja.i.ibm@gmail.com>
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Date: Thu, 9 Apr 2020 21:34:30 -0500
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Subject: [PATCH] [PowerPC] Bail out of redundant LI elimination on an implicit
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kill
6+
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The transformation currently does not differentiate between explicit
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and implicit kills. However, it is not valid to later simply clear
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an implicit kill flag since the kill could be due to a call or return.
10+
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Fixes: https://bugs.llvm.org/show_bug.cgi?id=45374
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---
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.../lib/Target/PowerPC/PPCPreEmitPeephole.cpp | 10 ++
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.../remove-redundant-li-skip-imp-kill.mir | 114 ++++++++++++++++++
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2 files changed, 124 insertions(+)
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create mode 100644 llvm/test/CodeGen/PowerPC/remove-redundant-li-skip-imp-kill.mir
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diff --git llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
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index a4b4bf2973d..4ea714ff15f 100644
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--- llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
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+++ llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
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@@ -109,6 +109,16 @@ namespace {
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// Track the operand that kill Reg. We would unset the kill flag of
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// the operand if there is a following redundant load immediate.
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int KillIdx = AfterBBI->findRegisterUseOperandIdx(Reg, true, TRI);
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+
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+ // We can't just clear implicit kills, so if we encounter one, stop
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+ // looking further.
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+ if (KillIdx != -1 && AfterBBI->getOperand(KillIdx).isImplicit()) {
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+ LLVM_DEBUG(dbgs()
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+ << "Encountered an implicit kill, cannot proceed: ");
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+ LLVM_DEBUG(AfterBBI->dump());
33+
+ break;
34+
+ }
35+
+
36+
if (KillIdx != -1) {
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assert(!DeadOrKillToUnset && "Shouldn't kill same register twice");
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DeadOrKillToUnset = &AfterBBI->getOperand(KillIdx);
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diff --git llvm/test/CodeGen/PowerPC/remove-redundant-li-skip-imp-kill.mir llvm/test/CodeGen/PowerPC/remove-redundant-li-skip-imp-kill.mir
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new file mode 100644
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index 00000000000..78091d027ce
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--- /dev/null
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+++ llvm/test/CodeGen/PowerPC/remove-redundant-li-skip-imp-kill.mir
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@@ -0,0 +1,114 @@
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+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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+# RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -run-pass \
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+# RUN: ppc-pre-emit-peephole %s -o - | FileCheck %s
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+--- |
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+ ; ModuleID = 'a.ll'
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+ source_filename = "a.ll"
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+ target datalayout = "e-m:e-i64:64-n32:64"
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+
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+ ; Function Attrs: nounwind
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+ define dso_local signext i32 @b(i32 signext %a, i32* nocapture %b) local_unnamed_addr #0 {
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+ entry:
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+ %call = tail call signext i32 @g(i32 signext %a)
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+ store i32 %call, i32* %b, align 4
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+ %call1 = tail call signext i32 @g(i32 signext %a)
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+ ret i32 %call1
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+ }
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+
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+ ; Function Attrs: nounwind
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+ declare signext i32 @g(i32 signext) local_unnamed_addr #0
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+
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+ ; Function Attrs: nounwind
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+ declare void @llvm.stackprotector(i8*, i8**) #0
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+
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+ attributes #0 = { nounwind }
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+
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+...
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+---
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+name: b
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+alignment: 16
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+exposesReturnsTwice: false
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+legalized: false
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+regBankSelected: false
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+selected: false
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+failedISel: false
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+tracksRegLiveness: true
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+hasWinCFI: false
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+registers: []
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+liveins:
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+ - { reg: '$x3', virtual-reg: '' }
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+ - { reg: '$x4', virtual-reg: '' }
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+frameInfo:
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+ isFrameAddressTaken: false
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+ isReturnAddressTaken: false
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+ hasStackMap: false
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+ hasPatchPoint: false
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+ stackSize: 64
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+ offsetAdjustment: 0
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+ maxAlignment: 1
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+ adjustsStack: true
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+ hasCalls: true
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+ stackProtector: ''
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+ maxCallFrameSize: 32
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+ cvBytesOfCalleeSavedRegisters: 0
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+ hasOpaqueSPAdjustment: false
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+ hasVAStart: false
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+ hasMustTailInVarArgFunc: false
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+ localFrameSize: 0
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+ savePoint: ''
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+ restorePoint: ''
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+fixedStack:
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+ - { id: 0, type: spill-slot, offset: -80, size: 8, alignment: 16, stack-id: default,
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+ callee-saved-register: '$x30', callee-saved-restored: true, debug-info-variable: '',
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+ debug-info-expression: '', debug-info-location: '' }
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+ - { id: 1, type: spill-slot, offset: -88, size: 8, alignment: 8, stack-id: default,
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+ callee-saved-register: '$x29', callee-saved-restored: true, debug-info-variable: '',
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+ debug-info-expression: '', debug-info-location: '' }
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+stack: []
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+callSites: []
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+constants: []
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+machineFunctionInfo: {}
115+
+body: |
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+ bb.0.entry:
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+ liveins: $x3, $x4, $x29, $x30
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+
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+ ; CHECK-LABEL: name: b
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+ ; CHECK: liveins: $x3, $x4, $x29, $x30
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+ ; CHECK: $x0 = MFLR8 implicit $lr8
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+ ; CHECK: STD killed $x29, -24, $x1 :: (store 8 into %fixed-stack.0)
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+ ; CHECK: STD killed $x30, -16, $x1 :: (store 8 into %fixed-stack.1, align 16)
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+ ; CHECK: STD killed $x0, 16, $x1
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+ ; CHECK: $x1 = STDU $x1, -64, $x1
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+ ; CHECK: $x30 = OR8 killed $x4, $x4
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+ ; CHECK: dead $r4 = LI 10, implicit-def $x4
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+ ; CHECK: $x29 = OR8 $x3, $x3
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+ ; CHECK: BL8_NOP @g, csr_ppc64_r2_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit $x2, implicit-def $r1, implicit-def $x3
130+
+ ; CHECK: STW8 killed renamable $x3, 0, killed renamable $x30 :: (store 4 into %ir.b)
131+
+ ; CHECK: $x3 = OR8 killed $x29, $x29
132+
+ ; CHECK: BL8_NOP @g, csr_ppc64_r2_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3
133+
+ ; CHECK: $x1 = ADDI8 $x1, 64
134+
+ ; CHECK: $x0 = LD 16, $x1
135+
+ ; CHECK: $x30 = LD -16, $x1 :: (load 8 from %fixed-stack.1, align 16)
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+ ; CHECK: $x29 = LD -24, $x1 :: (load 8 from %fixed-stack.0)
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+ ; CHECK: MTLR8 killed $x0, implicit-def $lr8
138+
+ ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
139+
+ $x0 = MFLR8 implicit $lr8
140+
+ STD killed $x29, -24, $x1 :: (store 8 into %fixed-stack.1)
141+
+ STD killed $x30, -16, $x1 :: (store 8 into %fixed-stack.0, align 16)
142+
+ STD killed $x0, 16, $x1
143+
+ $x1 = STDU $x1, -64, $x1
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+ $x30 = OR8 killed $x4, $x4
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+ dead $r4 = LI 10, implicit-def $x4
146+
+ $x29 = OR8 $x3, $x3
147+
+ BL8_NOP @g, csr_ppc64_r2_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit $x2, implicit-def $r1, implicit-def $x3
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+ STW8 killed renamable $x3, 0, killed renamable $x30 :: (store 4 into %ir.b)
149+
+ $x3 = OR8 killed $x29, $x29
150+
+ BL8_NOP @g, csr_ppc64_r2_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3
151+
+ $x1 = ADDI8 $x1, 64
152+
+ $x0 = LD 16, $x1
153+
+ $x30 = LD -16, $x1 :: (load 8 from %fixed-stack.0, align 16)
154+
+ $x29 = LD -24, $x1 :: (load 8 from %fixed-stack.1)
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+ MTLR8 killed $x0, implicit-def $lr8
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+ BLR8 implicit $lr8, implicit $rm, implicit killed $x3
157+
+
158+
+...
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--
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2.26.0
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‎deps/patches/llvm-10.0-PPC_SELECT_CC.patch

Lines changed: 135 additions & 0 deletions
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@@ -0,0 +1,135 @@
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From 4765db99fa35257a4209e2976903d81087a3f0d7 Mon Sep 17 00:00:00 2001
2+
From: Nemanja Ivanovic <nemanja.i.ibm@gmail.com>
3+
Date: Thu, 9 Apr 2020 13:53:02 -0500
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Subject: [PATCH] [PowerPC] Don't assert on SELECT_CC with i1 type
5+
6+
When we try to select a SELECT_CC on Power9, we check if it can be matched to a
7+
SETB instruction. In that function, we assert that the output type is i32/i64.
8+
This is unnecessary as it is perfectly reasonable to have an i1 SELECT_CC.
9+
Change that from an assert to an early exit condition.
10+
Fixes: https://bugs.llvm.org/show_bug.cgi?id=45448
11+
---
12+
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 7 +-
13+
llvm/test/CodeGen/PowerPC/pr45448.ll | 90 +++++++++++++++++++++
14+
2 files changed, 92 insertions(+), 5 deletions(-)
15+
create mode 100644 llvm/test/CodeGen/PowerPC/pr45448.ll
16+
17+
diff --git llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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index 776ec52e260..9230ce4118b 100644
19+
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
20+
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
21+
@@ -4241,13 +4241,10 @@ static bool mayUseP9Setb(SDNode *N, const ISD::CondCode &CC, SelectionDAG *DAG,
22+
SDValue TrueRes = N->getOperand(2);
23+
SDValue FalseRes = N->getOperand(3);
24+
ConstantSDNode *TrueConst = dyn_cast<ConstantSDNode>(TrueRes);
25+
- if (!TrueConst)
26+
+ if (!TrueConst || (N->getSimpleValueType(0) != MVT::i64 &&
27+
+ N->getSimpleValueType(0) != MVT::i32))
28+
return false;
29+
30+
- assert((N->getSimpleValueType(0) == MVT::i64 ||
31+
- N->getSimpleValueType(0) == MVT::i32) &&
32+
- "Expecting either i64 or i32 here.");
33+
-
34+
// We are looking for any of:
35+
// (select_cc lhs, rhs, 1, (sext (setcc [lr]hs, [lr]hs, cc2)), cc1)
36+
// (select_cc lhs, rhs, -1, (zext (setcc [lr]hs, [lr]hs, cc2)), cc1)
37+
diff --git llvm/test/CodeGen/PowerPC/pr45448.ll llvm/test/CodeGen/PowerPC/pr45448.ll
38+
new file mode 100644
39+
index 00000000000..eb0a61cb075
40+
--- /dev/null
41+
+++ llvm/test/CodeGen/PowerPC/pr45448.ll
42+
@@ -0,0 +1,90 @@
43+
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
44+
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
45+
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
46+
+; RUN: FileCheck %s
47+
+define hidden void @julia_tryparse_internal_45896() #0 {
48+
+; CHECK-LABEL: julia_tryparse_internal_45896:
49+
+; CHECK: # %bb.0: # %top
50+
+; CHECK-NEXT: ld r3, 0(r3)
51+
+; CHECK-NEXT: cmpldi r3, 0
52+
+; CHECK-NEXT: beq cr0, .LBB0_3
53+
+; CHECK-NEXT: # %bb.1: # %top
54+
+; CHECK-NEXT: cmpldi r3, 10
55+
+; CHECK-NEXT: beq cr0, .LBB0_4
56+
+; CHECK-NEXT: # %bb.2: # %top
57+
+; CHECK-NEXT: .LBB0_3: # %fail194
58+
+; CHECK-NEXT: .LBB0_4: # %L294
59+
+; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_6
60+
+; CHECK-NEXT: # %bb.5: # %L294
61+
+; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_7
62+
+; CHECK-NEXT: .LBB0_6: # %L1057.preheader
63+
+; CHECK-NEXT: .LBB0_7: # %L670
64+
+; CHECK-NEXT: lis r5, 4095
65+
+; CHECK-NEXT: ori r5, r5, 65533
66+
+; CHECK-NEXT: sldi r5, r5, 4
67+
+; CHECK-NEXT: cmpdi r3, 0
68+
+; CHECK-NEXT: sradi r4, r3, 63
69+
+; CHECK-NEXT: mulhdu r3, r3, r5
70+
+; CHECK-NEXT: maddld r6, r4, r5, r3
71+
+; CHECK-NEXT: crnor 4*cr5+gt, eq, eq
72+
+; CHECK-NEXT: cmpld r6, r3
73+
+; CHECK-NEXT: mulld r3, r4, r5
74+
+; CHECK-NEXT: cmpldi cr1, r3, 0
75+
+; CHECK-NEXT: crandc 4*cr5+lt, lt, 4*cr1+eq
76+
+; CHECK-NEXT: mulhdu. r3, r4, r5
77+
+; CHECK-NEXT: bc 4, 4*cr5+gt, .LBB0_10
78+
+; CHECK-NEXT: # %bb.8: # %L670
79+
+; CHECK-NEXT: crorc 4*cr5+lt, 4*cr5+lt, eq
80+
+; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_10
81+
+; CHECK-NEXT: # %bb.9: # %L917
82+
+; CHECK-NEXT: .LBB0_10: # %L994
83+
+top:
84+
+ %0 = load i64, i64* undef, align 8
85+
+ %1 = icmp ne i64 %0, 0
86+
+ %2 = sext i64 %0 to i128
87+
+ switch i64 %0, label %pass195 [
88+
+ i64 10, label %L294
89+
+ i64 16, label %L294.fold.split
90+
+ i64 0, label %fail194
91+
+ ]
92+
+
93+
+L294.fold.split: ; preds = %top
94+
+ unreachable
95+
+
96+
+L294: ; preds = %top
97+
+ %3 = add nsw i32 0, -48
98+
+ %4 = zext i32 %3 to i128
99+
+ %5 = add i128 %4, 0
100+
+ switch i32 undef, label %L670 [
101+
+ i32 -1031471104, label %L1057.preheader
102+
+ i32 536870912, label %L1057.preheader
103+
+ ]
104+
+
105+
+L670: ; preds = %L294
106+
+ br label %L898
107+
+
108+
+L1057.preheader: ; preds = %L294, %L294
109+
+ unreachable
110+
+
111+
+L898: ; preds = %L670
112+
+ %umul = call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %2, i128 %5)
113+
+ %umul.ov = extractvalue { i128, i1 } %umul, 1
114+
+ %value_phi102 = and i1 %1, %umul.ov
115+
+ %6 = or i1 %value_phi102, false
116+
+ br i1 %6, label %L917, label %L994
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+
118+
+L917: ; preds = %L898
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+ unreachable
120+
+
121+
+L994: ; preds = %L898
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+ unreachable
123+
+
124+
+fail194: ; preds = %top
125+
+ unreachable
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+
127+
+pass195: ; preds = %top
128+
+ unreachable
129+
+}
130+
+
131+
+; Function Attrs: nounwind readnone speculatable willreturn
132+
+declare { i128, i1 } @llvm.umul.with.overflow.i128(i128, i128) #1
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--
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2.26.0
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