Move to new os-boot.

  Fix riscv#580

Signed-off-by: Ariel Xiong <ArielHeleneto@outlook.com>
Co-authored-by: Tim Hutt <tdhutt@gmail.com>

Author: Arielfoever

os-boot/README.md

@@ -9,50 +9,137 @@ interrupt controller). Console input is not currently supported.
 32-bit OS boots require a workaround for the 64-bit HTIF interface,
 which is currently not supported.
 
-OS boots use device-tree binary blobs generated by the `dtc` compiler,
-installable on Ubuntu and Debian machines with
+## Boot with prebuild ELF
 
-```
-sudo apt install device-tree-compiler
-```
+This ELF is built with these materials.
 
-## Booting Linux with the C backend
+- [Linux 6.14.4](https://cdn.kernel.org/pub/linux/kernel/v6.x/linux-6.14.4.tar.xz)
+- [riscv-collab/riscv-gnu-toolchain](https://github.com/riscv-collab/riscv-gnu-toolchain/commit/d0193d173cb43468b1ddf3f3a4ea57950b4a4a8c)
+- [riscv-software-src/opensbi](https://github.com/riscv-software-src/opensbi/commit/99aabc6b8431a2bcf2b28a2423952e529de9fbc5)
 
-The C model needs an ELF-version of the BBL (Berkeley-Boot-Loader)
-that contains the Linux kernel as an embedded payload. It also needs
-a DTB (device-tree blob) file describing the platform (say in the file
-`spike.dtb`). Once those are available (see below for suggestions),
-the model should be run as:
+### Build dtb
 
+```bash
+dtc < sos-boot/ail.dts > os-boot/sail.dtb
 ```
-$ ./c_emulator/riscv_sim_<arch> -t console.log -b spike.dtb bbl > execution-trace.log 2>&1 &
-$ tail -f console.log
+
+### Boot ELF
+
+```bash
+build/c_emulator/riscv_sim_rv64d -t /tmp/console.log --no-trace -p --device-tree-blob os-boot/sail.dtb os-boot/fw_payload.elf
 ```
 
-The `console.log` file contains the console boot messages. For maximum
-performance and benchmarking a model without any execution tracing is
-available on the optimize branch (`git checkout optimize`) of this
-repository. This currently requires the latest Sail built from source.
+Use `tail -f /tmp/console.log` to see the terminal log.
+
+### Results
+
+```log
+[ariel@archlinux sail-riscv]$ cat /tmp/console.log
 
-## Caveats for OS boot
+OpenSBI v1.6
+   ____                    _____ ____ _____
+  / __ \                  / ____|  _ \_   _|
+ | |  | |_ __   ___ _ __ | (___ | |_) || |
+ | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
+ | |__| | |_) |  __/ | | |____) | |_) || |_
+  \____/| .__/ \___|_| |_|_____/|____/_____|
+        | |
+        |_|
 
-- Some OS toolchains generate obsolete LR/SC instructions with now
-  illegal combinations of `.aq` and `.rl` flags. You can work-around
-  this by changing `riscv_mem.sail` to accept these flags.
+Platform Name               : ucbbar,spike-bare
+Platform Features           : medeleg
+Platform HART Count         : 1
+Platform IPI Device         : aclint-mswi
+Platform Timer Device       : aclint-mtimer @ 10000000Hz
+Platform Console Device     : htif
+Platform HSM Device         : ---
+Platform PMU Device         : ---
+Platform Reboot Device      : htif
+Platform Shutdown Device    : htif
+Platform Suspend Device     : ---
+Platform CPPC Device        : ---
+Firmware Base               : 0x80000000
+Firmware Size               : 317 KB
+Firmware RW Offset          : 0x40000
+Firmware RW Size            : 61 KB
+Firmware Heap Offset        : 0x46000
+Firmware Heap Size          : 37 KB (total), 2 KB (reserved), 11 KB (used), 23 KB (free)
+Firmware Scratch Size       : 4096 B (total), 392 B (used), 3704 B (free)
+Runtime SBI Version         : 2.0
+Standard SBI Extensions     : time,rfnc,ipi,base,hsm,srst,pmu,dbcn,legacy
+Experimental SBI Extensions : fwft,sse
 
-- One needs to manually ensure that the DTB used for the C model
-  accurately describes the physical memory map implemented in the C
-  platform. This will not be needed once the C model can generate its
-  own DTB.
+Domain0 Name                : root
+Domain0 Boot HART           : 0
+Domain0 HARTs               : 0*
+Domain0 Region00            : 0x0000000000000000-0x0000000000000fff M: (I,R,W) S/U: (R,W)
+Domain0 Region01            : 0x0000000080040000-0x000000008004ffff M: (R,W) S/U: ()
+Domain0 Region02            : 0x0000000002080000-0x00000000020bffff M: (I,R,W) S/U: ()
+Domain0 Region03            : 0x0000000080000000-0x000000008003ffff M: (R,X) S/U: ()
+Domain0 Region04            : 0x0000000002000000-0x000000000207ffff M: (I,R,W) S/U: ()
+Domain0 Region05            : 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X)
+Domain0 Next Address        : 0x0000000080200000
+Domain0 Next Arg1           : 0x0000000082200000
+Domain0 Next Mode           : S-mode
+Domain0 SysReset            : yes
+Domain0 SysSuspend          : yes
 
-## Sample Linux image
+Boot HART ID                : 0
+Boot HART Domain            : root
+Boot HART Priv Version      : v1.12
+Boot HART Base ISA          : rv64imafdcbv
+Boot HART ISA Extensions    : sscofpmf,zicntr,zihpm,smcntrpmf,sdtrig
+Boot HART PMP Count         : 16
+Boot HART PMP Granularity   : 2 bits
+Boot HART PMP Address Bits  : 54
+Boot HART MHPM Info         : 29 (0xfffffff8)
+Boot HART Debug Triggers    : 0 triggers
+Boot HART MIDELEG           : 0x0000000000002222
+Boot HART MEDELEG           : 0x000000000004b109
+[    0.000000] Linux version 6.14.4 (ariel@archlinux) (riscv64-unknown-linux-gnu-gcc (g04696df09) 14.2.0, GNU ld (GNU Binutils) 2.44) #1 SMP Sat Apr 26 14:42:54 CST 2025
+[    0.000000] Machine model: ucbbar,spike-bare
+[    0.000000] SBI specification v2.0 detected
+[    0.000000] SBI implementation ID=0x1 Version=0x10006
+[    0.000000] SBI TIME extension detected
+[    0.000000] SBI IPI extension detected
+[    0.000000] SBI RFENCE extension detected
+[    0.000000] SBI SRST extension detected
+[    0.000000] SBI DBCN extension detected
+[    0.000000] earlycon: sbi0 at I/O port 0x0 (options '')
+[    0.000000] printk: legacy bootconsole [sbi0] enabled
+[    0.000000] efi: UEFI not found.
+[    0.000000] OF: reserved mem: 0x0000000080000000..0x000000008003ffff (256 KiB) nomap non-reusable mmode_resv1@80000000
+[    0.000000] OF: reserved mem: 0x0000000080040000..0x000000008004ffff (64 KiB) nomap non-reusable mmode_resv0@80040000
+[    0.000000] Zone ranges:
+[    0.000000]   DMA32    [mem 0x0000000080000000-0x00000000ffffffff]
+[    0.000000]   Normal   empty
+[    0.000000] Movable zone start for each node
+[    0.000000] Early memory node ranges
+[    0.000000]   node   0: [mem 0x0000000080000000-0x000000008004ffff]
+[    0.000000]   node   0: [mem 0x0000000080050000-0x00000000ffffffff]
+[    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000000ffffffff]
+```
+
+## Build your own ELF
 
-`rv64-linux-4.15.0-gcc-7.2.0-64mb.bbl` contains a sample Linux RV64
-image that can be booted as follows, after first generating the
-device-tree blob for a 64MB RV64 machine using `dtc`:
+### Build Kernel Image
 
+```bash
+wget https://cdn.kernel.org/pub/linux/kernel/v6.x/linux-6.14.4.tar.xz
+tar -xzf linux-6.14.4.tar.xz
+cd linux-6.14.4
+make ARCH=riscv CROSS_COMPILE=../toolchain/riscv64-unknown-linux-gnu- defconfig
+make ARCH=riscv CROSS_COMPILE=../toolchain/riscv64-unknown-linux-gnu- Image vmlinux
 ```
-dtc < os-boot/rv64-64mb.dts > os-boot/rv64-64mb.dtb
-./c_emulator/riscv_sim_RV64 -b os-boot/rv64-64mb.dtb -t /tmp/console.log os-boot/rv64-linux-4.15.0-gcc-7.2.0-64mb.bbl > >(gzip -c > execution-trace.log.gz) 2>&1
-tail -f /tmp/console.log
+
+This will generate `arch/riscv/boot/Image` which will be a part of payload.
+
+### Build openSBI
+
+```bash
+git clone https://github.com/riscv-software-src/opensbi --depth=1
+cd opensbi
+make FW_TEXT_START=0x80000000 FW_PAYLOAD=y FW_PAYLOAD_PATH=../linux-6.14.4/arch/riscv/boot/Image CROSS_COMPILE=../toolchain/riscv64-unknown-linux-gnu- PLATFORM=generic
 ```
+
+This will generate `build/platform/generic/firmware/fw_payload.elf`.

os-boot/freebsd-rv64.bbl renamed to os-boot/fw_payload.elf

@@ -5,6 +5,9 @@
   #size-cells = <2>;
   compatible = "ucbbar,spike-bare-dev";
   model = "ucbbar,spike-bare";
+  chosen {
+    bootargs = "console=hvc0 earlycon=sbi";
+  };
   cpus {
     #address-cells = <1>;
     #size-cells = <0>;
@@ -14,10 +17,13 @@
       reg = <0>;
       status = "okay";
       compatible = "riscv";
-      riscv,isa = "rv64imac";
+      riscv,isa = "rv64imafd";
       mmu-type = "riscv,sv39";
+      riscv,pmpregions = <16>;
+      riscv,pmpgranularity = <4>;
       clock-frequency = <1000000000>;
       CPU0_intc: interrupt-controller {
+        #address-cells = <2>;
         #interrupt-cells = <1>;
         interrupt-controller;
         compatible = "riscv,cpu-intc";