aarch64: setup logging and DTB structure

Signed-off-by: Andy-Python-Programmer <andypythonappdeveloper@gmail.com>

Author: Andy-Python-Programmer

src/Cargo.lock

@@ -0,0 +1,29 @@
+#[derive(Debug)]
+#[repr(C)]
+struct FdtHeader {
+    magic: u32,
+    totalsize: u32,
+    off_dt_struct: u32,
+    off_dt_strings: u32,
+    off_mem_rsvmap: u32,
+    version: u32,
+    last_comp_version: u32,
+    boot_cpuid_phys: u32,
+    size_dt_strings: u32,
+    size_dt_struct: u32,
+}
+
+pub struct Dtb<'a> {
+    header: &'a FdtHeader,
+}
+
+impl<'a> Dtb<'a> {
+    pub fn new(blob: *const u8) -> Self {
+        let header = unsafe { &*(blob as *const FdtHeader) };
+        // assert_eq!(header.magic, 0xd00dfeed);
+
+        log::debug!("{header:#x?}");
+
+        Self { header }
+    }
+}

src/aero_kernel/src/arch/aarch64/dtb.rs

@@ -45,18 +45,22 @@ pub fn register_handler(vector: u8, handler: fn(&mut InterruptStack)) {
     unimplemented!()
 }
 
-pub unsafe fn disable_interrupts() {
-    unimplemented!()
+pub fn is_enabled() -> bool {
+    let v: u64;
+    unsafe {
+        asm!("mrs {}, daif", out(reg) v, options(nostack, nomem));
+    }
+    (!v) != 0
 }
 
-pub fn is_enabled() -> bool {
-    unimplemented!()
+pub unsafe fn disable_interrupts() {
+    asm!("msr daifset, #15", options(nomem, nostack))
 }
 
 pub unsafe fn enable_interrupts() {
-    unimplemented!()
+    asm!("msr daifclr, #15", options(nomem, nostack))
 }
 
 pub unsafe fn halt() {
-    asm!("wfi");
+    asm!("wfi", options(nomem, nostack));
 }

src/aero_kernel/src/arch/aarch64/interrupts.rs

@@ -17,22 +17,72 @@
  * along with Aero. If not, see <https://www.gnu.org/licenses/>.
  */
 
+pub mod dtb;
 pub mod interrupts;
 pub mod task;
 pub mod time;
 pub mod tls;
 
+use crate::{drivers, logger};
+
 use limine::*;
 
+use crate::mem::paging::VirtAddr;
+
 static TERMINAL: LimineTerminalRequest = LimineTerminalRequest::new(0);
+static HHDM: LimineHhdmRequest = LimineHhdmRequest::new(0);
+static KERNEL_FILE: LimineKernelFileRequest = LimineKernelFileRequest::new(0);
+static DTB: LimineDtbRequest = LimineDtbRequest::new(0);
 
 #[no_mangle]
 extern "C" fn arch_aero_main() -> ! {
-    let response = TERMINAL.get_response().get().unwrap();
-    let terminal = &response.terminals()[0];
-    let writer = response.write().unwrap();
+    unsafe {
+        interrupts::disable_interrupts();
+    }
+
+    unsafe {
+        crate::PHYSICAL_MEMORY_OFFSET = VirtAddr::new(HHDM.get_response().get().unwrap().offset);
+    }
+
+    let kernel_file_resp = KERNEL_FILE
+        .get_response()
+        .get()
+        .expect("limine: invalid kernel file response");
+
+    let kernel_file = kernel_file_resp
+        .kernel_file
+        .get()
+        .expect("limine: invalid kernel file pointer");
+
+    // Before we start the initialization process, we need to make sure
+    // the unwind info is avaliable; just in case if there is a kernel
+    // panic, it will be able to unwind the stack.
+    crate::unwind::UNWIND_INFO.call_once(|| {
+        use crate::unwind::UnwindInfo;
+        use xmas_elf::ElfFile;
+
+        let start = kernel_file
+            .base
+            .as_ptr()
+            .expect("limine: invalid kernel file base");
+
+        // SAFETY: The bootloader will provide a valid pointer to the kernel file.
+        let elf_slice = unsafe { core::slice::from_raw_parts(start, kernel_file.length as usize) };
+        let elf = ElfFile::new(elf_slice).expect("limine: invalid kernel file");
+
+        UnwindInfo::new(elf)
+    });
+
+    // Now that we have unwind info, we can initialize the COM ports. This
+    // will be used to print panic messages/logs before the debug renderer is
+    // initialized to the serial output (if avaliable).
+    drivers::uart::init();
+    logger::init();
 
-    writer(&terminal, "Hello Aero from unbased64 booted by limine :^)");
+    log::debug!("lmao");
+    let dtb_response = DTB.get_response().get().unwrap();
+    let dtb_blob = dtb_response.dtb_ptr.as_ptr().unwrap();
+    let dtb = dtb::Dtb::new(dtb_blob);
 
     loop {}
 }

src/aero_kernel/src/arch/aarch64/mod.rs

@@ -37,7 +37,7 @@ cfg_if::cfg_if! {
         pub mod uart_16550;
         pub use self::uart_16550 as uart;
     } else if #[cfg(target_arch = "aarch64")] {
-        pub mod uart_mmio32;
-        pub use self::uart_mmio32 as uart;
+        pub mod uart_pl011;
+        pub use self::uart_pl011 as uart;
     }
 }

src/aero_kernel/src/drivers/mod.rs

@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2021-2022 The Aero Project Developers.
+ *
+ * This file is part of The Aero Project.
+ *
+ * Aero is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Aero is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Aero. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+// REFRENCE: PrimeCell UART (PL011) Technical Reference Manual
+
+use core::fmt;
+use core::fmt::Write;
+
+use spin::Once;
+
+use core::sync::atomic::{AtomicPtr, Ordering};
+
+use crate::mem::paging::VirtAddr;
+use crate::utils::sync::Mutex;
+
+static SERIAL: Once<Mutex<PrimeCellSerialPort>> = Once::new();
+
+pub struct PrimeCellSerialPort(*mut u8);
+
+impl PrimeCellSerialPort {
+    pub unsafe fn new(base: usize) -> Self {
+        let base_pointer = base as *mut u8;
+        Self(base_pointer)
+    }
+
+    unsafe fn write(&mut self, register: u8, value: u16) {
+        core::ptr::write_volatile(self.0.offset(register as isize) as *mut u16, value);
+    }
+
+    unsafe fn read(&self, register: u8) -> u16 {
+        core::ptr::read_volatile(self.0.offset(register as isize) as *mut u16)
+    }
+
+    pub fn init(mut self) -> Self {
+        unsafe {
+            // Enable RXE, TXE, UARTEN
+            self.write(0x30, 1 << 9 | 1 << 8 | 1 << 0);
+
+            // Disable FIFOs (use character mode instead)
+            let mut flags = self.read(0x2c);
+            flags &= !(1 << 4);
+
+            // Enable IRQs
+            self.write(0x38, 1 << 4);
+
+            // Clear pending interrupts
+            self.write(0x44, 0x7ff);
+        }
+
+        self
+    }
+
+    fn wait_transmit(&self) {
+        // TXFE - this bit is set when the transmit holding register is empty.
+        while unsafe { self.read(0x18) } & 1 << 7 != 1 << 7 {
+            core::hint::spin_loop();
+        }
+    }
+
+    pub fn send(&mut self, byte: u8) {
+        unsafe {
+            match byte {
+                8 | 0x7F => {
+                    self.wait_transmit();
+                    self.write(0, 8);
+
+                    self.wait_transmit();
+                    self.write(0, b' ' as _);
+
+                    self.wait_transmit();
+                    self.write(0, 8);
+                }
+
+                _ => {
+                    self.wait_transmit();
+                    self.write(0, byte as u16);
+                }
+            }
+        }
+    }
+}
+
+unsafe impl Send for PrimeCellSerialPort {}
+
+impl fmt::Write for PrimeCellSerialPort {
+    fn write_str(&mut self, s: &str) -> fmt::Result {
+        for byte in s.bytes() {
+            self.send(byte);
+        }
+        Ok(())
+    }
+}
+pub fn init() {
+    // CC: https://github.com/limine-bootloader/limine/issues/215
+    let mut serial = unsafe { PrimeCellSerialPort::new(0x9000000) }.init();
+    SERIAL.call_once(|| Mutex::new(serial));
+}
+
+pub macro serial_print($($arg:tt)*) {
+    crate::drivers::uart_pl011::_serial_print(format_args!($($arg)*))
+}
+
+pub macro serial_println {
+    () => ($crate::drivers::uart_pl011::serial_print!("\n")),
+    ($($arg:tt)*) => ($crate::drivers::uart_pl011::serial_print!("{}\n", format_args!($($arg)*)))
+}
+
+#[doc(hidden)]
+pub fn _serial_print(args: fmt::Arguments) {
+    SERIAL.get().map(|c| {
+        c.lock_irq()
+            .write_fmt(args)
+            .expect("failed to write to serial")
+    });
+}