block: GPT

* GPT

* NVME make use of PRP2 when the content cannot fit in 1 page (4096
bytes)

* NVME Completion Queue - make sure to return an error if has had one

* EXT2 framework

Signed-off-by: Andy-Python-Programmer <andypythonappdeveloper@gmail.com>

Author: Andy-Python-Programmer

src/aero_kernel/src/drivers/block/ide/mod.rs

@@ -20,6 +20,8 @@
 mod channel;
 mod registers;
 
+use core::mem::MaybeUninit;
+
 use channel::*;
 
 use alloc::sync::Arc;
@@ -50,14 +52,15 @@ impl IdeDrive {
 }
 
 impl BlockDeviceInterface for IdeDrive {
-    fn read(&self, sector: usize, dest: &mut [u8]) -> Option<usize> {
+    fn read(&self, sector: usize, dest: &mut [MaybeUninit<u8>]) -> Option<usize> {
         let count = dest.len().ceil_div(512);
         let request = Arc::new(DmaRequest::new(sector, count));
 
         let res = self.channel.run_request(request.clone(), self.slave);
 
         if res.is_some() {
-            request.copy_into(dest);
+            todo!()
+            // request.copy_into(dest);
         }
 
         res

src/aero_kernel/src/drivers/block/nvme/command.rs

@@ -17,8 +17,6 @@
  * along with Aero. If not, see <https://www.gnu.org/licenses/>.
  */
 
-use bit_field::BitField;
-
 #[repr(u8)]
 #[derive(Default, Copy, Clone)]
 pub enum IdentifyCns {
@@ -58,7 +56,7 @@ pub enum AdminOpcode {
     Unknown = u8::MAX,
 }
 
-#[derive(Default, Copy, Clone)]
+#[derive(Debug, Default, Copy, Clone)]
 #[repr(C)]
 pub struct DataPointer {
     pub prp1: u64,
@@ -272,7 +270,7 @@ pub struct IdentifyNamespace {
 const_assert_eq!(core::mem::size_of::<IdentifyNamespace>(), 0x1000);
 
 #[repr(C)]
-#[derive(Default, Copy, Clone)]
+#[derive(Debug, Default, Copy, Clone)]
 pub struct ReadWriteCommand {
     pub opcode: u8,
     pub flags: u8,
@@ -343,16 +341,12 @@ impl Into<Command> for CreateCQCommand {
 #[derive(Clone, Copy, Debug)]
 #[repr(C)]
 pub struct CompletionEntry {
-    dw0: u32,
-    dw1: u32,
-    dw2: u32,
-    dw3: u32,
-}
-
-impl CompletionEntry {
-    pub fn get_phase_tag(&self) -> bool {
-        self.dw3.get_bit(16)
-    }
+    pub result: u32, // Used by admin commands to return data.
+    pub reserved: u32,
+    pub sq_head: u16,    // Portion of the queue that may be reclaimed
+    pub sq_id: u16,      // Submission Queue that generated this entry.
+    pub command_id: u16, // Command ID of the command that was completed.
+    pub status: u16,     // Reason why the command failed, if it did.
 }
 
 #[repr(C)]

src/aero_kernel/src/drivers/block/nvme/dma.rs

@@ -35,22 +35,26 @@ pub struct DmaAllocator;
 unsafe impl Allocator for DmaAllocator {
     fn allocate(&self, layout: Layout) -> Result<NonNull<[u8]>, AllocError> {
         // XXX: The DMA buffer must be aligned to a page boundary.
-        let size = align_up(layout.size() as u64, Size2MiB::SIZE);
+        let size_bytes = layout.size() as u64;
 
-        let pages = size / Size2MiB::SIZE;
-        assert!(pages == 1);
+        let phys = if size_bytes <= Size4KiB::SIZE {
+            let frame: PhysFrame<Size4KiB> = FRAME_ALLOCATOR.allocate_frame().ok_or(AllocError)?;
+            frame.start_address()
+        } else {
+            assert!(size_bytes <= Size2MiB::SIZE);
 
-        let frame: PhysFrame<Size2MiB> = FRAME_ALLOCATOR.allocate_frame().ok_or(AllocError)?;
-        let virt = frame.start_address().as_hhdm_virt();
+            let frame: PhysFrame<Size2MiB> = FRAME_ALLOCATOR.allocate_frame().ok_or(AllocError)?;
+            frame.start_address()
+        };
+
+        let virt = phys.as_hhdm_virt();
 
         // SAFETY: The frame is aligned and non-null.
         let ptr = unsafe { NonNull::new_unchecked(virt.as_mut_ptr() as *mut u8) };
-        Ok(NonNull::slice_from_raw_parts(ptr, size as _))
+        Ok(NonNull::slice_from_raw_parts(ptr, size_bytes as _))
     }
 
-    unsafe fn deallocate(&self, _ptr: NonNull<u8>, _layout: Layout) {
-        log::warn!("DMA memory deallocation is not *yet* implemented :) Enjoy the leaks :)")
-    }
+    unsafe fn deallocate(&self, _ptr: NonNull<u8>, _layout: Layout) {}
 }
 
 pub type DmaBuffer<T> = Box<T, DmaAllocator>;

src/aero_kernel/src/drivers/block/nvme/mod.rs

@@ -21,6 +21,8 @@ mod command;
 mod dma;
 mod queue;
 
+use core::mem::MaybeUninit;
+
 use command::*;
 use dma::*;
 use queue::*;
@@ -36,7 +38,7 @@ use crate::fs::block::{install_block_device, BlockDevice, BlockDeviceInterface};
 use crate::mem::paging::*;
 
 use crate::utils::sync::Mutex;
-use crate::utils::VolatileCell;
+use crate::utils::{CeilDiv, VolatileCell};
 
 #[derive(Copy, Clone, Debug)]
 enum Error {
@@ -78,7 +80,8 @@ bitflags::bitflags! {
 struct Capability(VolatileCell<u64>);
 
 impl Capability {
-    /// Returns maximum individual queue size that the controller supports.
+    /// Returns maximum individual queue size that the controller
+    /// supports.
     fn max_queue_entries(&self) -> u16 {
         self.0.get().get_bits(0..16) as u16
     }
@@ -88,10 +91,17 @@ impl Capability {
         self.0.get().get_bits(32..36)
     }
 
-    /// Returns the command sets that are supported by the controller.
+    /// Returns the command sets that are supported by the
+    /// controller.
     fn get_css(&self) -> CommandSetsSupported {
         CommandSetsSupported::from_bits_truncate(self.0.get().get_bits(37..45) as u8)
     }
+
+    /// Returns the the minimum host memory page size that the
+    /// controller supports.
+    fn mpsmin(&self) -> u64 {
+        self.0.get().get_bits(48..52)
+    }
 }
 
 #[repr(u32)]
@@ -215,27 +225,48 @@ struct Namespace<'a> {
     blocks: usize,
     block_size: usize,
     size: usize,
+    max_prps: usize,
+    prps: Mutex<Dma<[MaybeUninit<u64>]>>,
     controller: Arc<Controller<'a>>,
 }
 
 impl<'a> Namespace<'a> {
-    fn read(&self, sector: usize, dest: &mut [u8]) {
-        let length = ((dest.len() / self.block_size) - 1) as u16;
+    fn read(&self, sector: usize, dest: &mut [MaybeUninit<u8>]) {
+        let size_bytes = dest.len();
+        let blocks = size_bytes.ceil_div(self.block_size);
 
         let buffer = Dma::<u8>::new_uninit_slice(dest.len());
         let mut read_cmd = ReadWriteCommand::default();
 
         read_cmd.opcode = CommandOpcode::Read as u8;
         read_cmd.nsid = self.nsid;
         read_cmd.start_lba = sector as u64;
-        read_cmd.length = length;
-        read_cmd.data_ptr.prp1 = buffer.addr().as_u64();
+        read_cmd.length = (blocks - 1) as u16;
+
+        if size_bytes > Size4KiB::SIZE as usize {
+            // The data cannot fit in 8KiB frames, so we need to use
+            // a PRP list.
+            let prp_num = ((blocks - 1) * self.block_size) / Size4KiB::SIZE as usize;
+            assert!(prp_num < self.max_prps);
+
+            let mut prps = self.prps.lock();
+
+            for i in 0..prp_num {
+                prps[i]
+                    .write((buffer.addr().as_u64() + Size4KiB::SIZE) + (Size4KiB::SIZE * i as u64));
+            }
+
+            read_cmd.data_ptr.prp1 = buffer.addr().as_u64();
+            read_cmd.data_ptr.prp2 = prps.addr().as_u64();
+        } else {
+            read_cmd.data_ptr.prp1 = buffer.addr().as_u64();
+        }
 
         self.controller.io_queue.lock().submit_command(read_cmd);
 
         // SAFETY: The buffer is initialized above.
         let buffer = unsafe { buffer.assume_init() };
-        dest.copy_from_slice(&*buffer);
+        MaybeUninit::write_slice(dest, &*buffer);
     }
 }
 
@@ -356,6 +387,13 @@ impl<'a> Controller<'a> {
 
         admin.submit_command(io_sq_cmd);
 
+        let shift = 12 + registers.capability.mpsmin() as usize;
+        let max_transfer_shift = if identity.mdts != 0 {
+            shift + identity.mdts as usize
+        } else {
+            20
+        };
+
         let this = Arc::new(Self {
             identity,
             namespaces: Mutex::new(alloc::vec![]),
@@ -396,12 +434,19 @@ impl<'a> Controller<'a> {
                 let blocks = identity.nsze as usize;
                 let block_size = 1 << identity.lbaf[(identity.flbas & 0b11111) as usize].ds;
 
+                // The maximum transfer size is in units of 2^(min page size)
+                let lba_shift = identity.lbaf[(identity.flbas & 0xf) as usize].ds;
+                let max_lbas = 1 << (max_transfer_shift - lba_shift as usize);
+                let max_prps = (max_lbas * (1 << lba_shift)) / Size4KiB::SIZE as usize;
+
                 Namespace {
                     controller: this.clone(),
                     nsid: *nsid,
                     blocks,
                     block_size,
                     size: blocks * block_size,
+                    max_prps,
+                    prps: Mutex::new(Dma::new_uninit_slice(max_prps)),
                 }
             })
             .collect::<Vec<_>>();
@@ -423,7 +468,7 @@ impl<'a> Controller<'a> {
 }
 
 impl<'a> BlockDeviceInterface for Controller<'a> {
-    fn read(&self, sector: usize, dest: &mut [u8]) -> Option<usize> {
+    fn read(&self, sector: usize, dest: &mut [MaybeUninit<u8>]) -> Option<usize> {
         self.namespaces.lock()[0].read(sector, dest);
         Some(dest.len())
     }

src/aero_kernel/src/drivers/block/nvme/queue.rs

@@ -1,4 +1,4 @@
-use core::mem::MaybeUninit;
+use core::cell::UnsafeCell;
 use core::sync::atomic::{AtomicU16, Ordering};
 
 use crate::mem::paging::PhysAddr;
@@ -38,7 +38,7 @@ unsafe impl Sync for DoorBell {}
 pub(super) struct Queue<'bell, T: QueueType> {
     doorbell: &'bell DoorBell,
     index: usize,
-    queue: Dma<[MaybeUninit<T::Type>]>,
+    queue: Dma<[UnsafeCell<T::Type>]>,
     phase: bool,
 }
 
@@ -53,7 +53,7 @@ impl<'bell, T: QueueType> Queue<'bell, T> {
 
         Ok(Self {
             doorbell,
-            queue: Dma::new_uninit_slice(size),
+            queue: unsafe { Dma::new_uninit_slice(size).assume_init() },
             index: 0,
             phase: true,
         })
@@ -66,20 +66,30 @@ impl<'bell, T: QueueType> Queue<'bell, T> {
 
 impl Queue<'_, Completion> {
     pub fn next_cmd_result(&mut self) -> Option<CompletionEntry> {
-        let cur_completion = unsafe { self.queue[self.index].assume_init() };
-        if cur_completion.get_phase_tag() != self.phase {
-            self.index += 1;
-            self.doorbell.0.set(self.index as u32);
-            Some(cur_completion.clone())
-        } else {
-            None
+        let cmd = &mut self.queue[self.index];
+
+        while (cmd.get_mut().status & 0x1) != self.phase as u16 {
+            core::hint::spin_loop();
+        }
+
+        let cmd = cmd.get_mut();
+        let status = cmd.status >> 1;
+
+        if status != 0 {
+            log::error!("nvme: command error {status:#x}");
+            return None;
         }
+
+        self.index += 1;
+        self.doorbell.0.set(self.index as u32);
+
+        Some(cmd.clone())
     }
 }
 
 impl Queue<'_, Submisson> {
     pub fn submit_command(&mut self, command: Command) {
-        self.queue[self.index] = MaybeUninit::new(command);
+        self.queue[self.index] = UnsafeCell::new(command);
 
         self.index += 1;
         self.doorbell.0.set(self.index as u32); // ring ring!