RDMA/mlx5: Fix xlt_chunk_align calculation

niklas88 · jgunthorpe · commit f4c6f31011ea · 2021-09-08T08:31:10.000-03:00
The XLT chunk alignment depends on ent_size not sizeof(ent_size) aka sizeof(size_t). The incoming ent_size is either 8 or 16, so the miscalculation when 16 is required is only an over-alignment and functional harmless. Fixes: 8010d74 ("RDMA/mlx5: Split the WR setup out of mlx5_ib_update_xlt()") Link: https://lore.kernel.org/r/20210908081849.7948-2-schnelle@linux.ibm.com Signed-off-by: Niklas Schnelle <schnelle@linux.ibm.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
diff --git a/drivers/infiniband/hw/mlx5/mr.c b/drivers/infiniband/hw/mlx5/mr.c
@@ -995,7 +995,7 @@ static struct mlx5_ib_mr *alloc_cacheable_mr(struct ib_pd *pd,
 static void *mlx5_ib_alloc_xlt(size_t *nents, size_t ent_size, gfp_t gfp_mask)
 {
 	const size_t xlt_chunk_align =
-		MLX5_UMR_MTT_ALIGNMENT / sizeof(ent_size);
+		MLX5_UMR_MTT_ALIGNMENT / ent_size;
 	size_t size;
 	void *res = NULL;
 

Original file line number	Diff line number	Diff line change
`@@ -995,7 +995,7 @@ static struct mlx5_ib_mr alloc_cacheable_mr(struct ib_pd pd,`
`995`	`995`	`static void mlx5_ib_alloc_xlt(size_t nents, size_t ent_size, gfp_t gfp_mask)`
`996`	`996`	`{`
`997`	`997`	`const size_t xlt_chunk_align =`
`998`		`- MLX5_UMR_MTT_ALIGNMENT / sizeof(ent_size);`
	`998`	`+ MLX5_UMR_MTT_ALIGNMENT / ent_size;`
`999`	`999`	`size_t size;`
`1000`	`1000`	`void *res = NULL;`
`1001`	`1001`