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Merge tag 'drm-fixes-2021-07-23' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie: "Regular fixes - a bunch of amdgpu fixes are the main thing mostly for the new gpus. There is also some i915 reverts for older changes that were having some unwanted side effects. One nouveau fix for a report regressions, and otherwise just some misc fixes. core: - fix for non-drm ioctls on drm fd panel: - avoid double free ttm: - refcounting fix - NULL checks amdgpu: - Yellow Carp updates - Add some Yellow Carp DIDs - Beige Goby updates - CIK 10bit 4K regression fix - GFX10 golden settings updates - eDP panel regression fix - Misc display fixes - Aldebaran fix - fix COW checks nouveau: - init BO GEM fields i915: - revert async command parsing - revert fence error propogation - GVT fix for shadow ppgtt vc4: - fix interrupt handling" * tag 'drm-fixes-2021-07-23' of git://anongit.freedesktop.org/drm/drm: (34 commits) drm/panel: raspberrypi-touchscreen: Prevent double-free drm/amdgpu - Corrected the video codecs array name for yellow carp drm/amd/display: Fix ASSR regression on embedded panels drm/amdgpu: add yellow carp pci id (v2) drm/amdgpu: update yellow carp external rev_id handling drm/amd/pm: Support board calibration on aldebaran drm/amd/display: change zstate allow msg condition drm/amd/display: Populate dtbclk entries for dcn3.02/3.03 drm/amd/display: Line Buffer changes drm/amd/display: Remove MALL function from DCN3.1 drm/amd/display: Only set default brightness for OLED drm/amd/display: Update bounding box for DCN3.1 drm/amd/display: Query VCO frequency from register for DCN3.1 drm/amd/display: Populate socclk entries for dcn3.02/3.03 drm/amd/display: Fix max vstartup calculation for modes with borders drm/amd/display: implement workaround for riommu related hang drm/amd/display: Fix comparison error in dcn21 DML drm/i915: Correct the docs for intel_engine_cmd_parser drm/ttm: add missing NULL checks drm/ttm: Force re-init if ttm_global_init() fails ...
2 parents e08100f + 2e41a66 commit 8baef63

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lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -619,6 +619,13 @@ struct amdgpu_video_codec_info {
619619
u32 max_level;
620620
};
621621

622+
#define codec_info_build(type, width, height, level) \
623+
.codec_type = type,\
624+
.max_width = width,\
625+
.max_height = height,\
626+
.max_pixels_per_frame = height * width,\
627+
.max_level = level,
628+
622629
struct amdgpu_video_codecs {
623630
const u32 codec_count;
624631
const struct amdgpu_video_codec_info *codec_array;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1190,6 +1190,10 @@ static const struct pci_device_id pciidlist[] = {
11901190
/* Van Gogh */
11911191
{0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU},
11921192

1193+
/* Yellow Carp */
1194+
{0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1195+
{0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1196+
11931197
/* Navy_Flounder */
11941198
{0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
11951199
{0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -255,6 +255,15 @@ static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_str
255255
if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
256256
return -EPERM;
257257

258+
/* Workaround for Thunk bug creating PROT_NONE,MAP_PRIVATE mappings
259+
* for debugger access to invisible VRAM. Should have used MAP_SHARED
260+
* instead. Clearing VM_MAYWRITE prevents the mapping from ever
261+
* becoming writable and makes is_cow_mapping(vm_flags) false.
262+
*/
263+
if (is_cow_mapping(vma->vm_flags) &&
264+
!(vma->vm_flags & (VM_READ | VM_WRITE | VM_EXEC)))
265+
vma->vm_flags &= ~VM_MAYWRITE;
266+
258267
return drm_gem_ttm_mmap(obj, vma);
259268
}
260269

‎drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3300,6 +3300,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3[] =
33003300
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
33013301
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
33023302
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3303+
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
33033304
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
33043305
SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
33053306
};
@@ -3379,6 +3380,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
33793380
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
33803381
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
33813382
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3383+
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
33823384
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
33833385
SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
33843386
SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
@@ -3445,6 +3447,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
34453447
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
34463448
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
34473449
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3450+
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
34483451
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
34493452
SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
34503453
SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020)

‎drivers/gpu/drm/amd/amdgpu/nv.c

Lines changed: 50 additions & 198 deletions
Original file line numberDiff line numberDiff line change
@@ -64,32 +64,13 @@
6464
#include "smuio_v11_0.h"
6565
#include "smuio_v11_0_6.h"
6666

67-
#define codec_info_build(type, width, height, level) \
68-
.codec_type = type,\
69-
.max_width = width,\
70-
.max_height = height,\
71-
.max_pixels_per_frame = height * width,\
72-
.max_level = level,
73-
7467
static const struct amd_ip_funcs nv_common_ip_funcs;
7568

7669
/* Navi */
7770
static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] =
7871
{
79-
{
80-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
81-
.max_width = 4096,
82-
.max_height = 2304,
83-
.max_pixels_per_frame = 4096 * 2304,
84-
.max_level = 0,
85-
},
86-
{
87-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
88-
.max_width = 4096,
89-
.max_height = 2304,
90-
.max_pixels_per_frame = 4096 * 2304,
91-
.max_level = 0,
92-
},
72+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
73+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
9374
};
9475

9576
static const struct amdgpu_video_codecs nv_video_codecs_encode =
@@ -101,55 +82,13 @@ static const struct amdgpu_video_codecs nv_video_codecs_encode =
10182
/* Navi1x */
10283
static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] =
10384
{
104-
{
105-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
106-
.max_width = 4096,
107-
.max_height = 4096,
108-
.max_pixels_per_frame = 4096 * 4096,
109-
.max_level = 3,
110-
},
111-
{
112-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
113-
.max_width = 4096,
114-
.max_height = 4096,
115-
.max_pixels_per_frame = 4096 * 4096,
116-
.max_level = 5,
117-
},
118-
{
119-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
120-
.max_width = 4096,
121-
.max_height = 4096,
122-
.max_pixels_per_frame = 4096 * 4096,
123-
.max_level = 52,
124-
},
125-
{
126-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
127-
.max_width = 4096,
128-
.max_height = 4096,
129-
.max_pixels_per_frame = 4096 * 4096,
130-
.max_level = 4,
131-
},
132-
{
133-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
134-
.max_width = 8192,
135-
.max_height = 4352,
136-
.max_pixels_per_frame = 8192 * 4352,
137-
.max_level = 186,
138-
},
139-
{
140-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
141-
.max_width = 4096,
142-
.max_height = 4096,
143-
.max_pixels_per_frame = 4096 * 4096,
144-
.max_level = 0,
145-
},
146-
{
147-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
148-
.max_width = 8192,
149-
.max_height = 4352,
150-
.max_pixels_per_frame = 8192 * 4352,
151-
.max_level = 0,
152-
},
85+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
86+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
87+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
88+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
89+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
90+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
91+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
15392
};
15493

15594
static const struct amdgpu_video_codecs nv_video_codecs_decode =
@@ -161,62 +100,14 @@ static const struct amdgpu_video_codecs nv_video_codecs_decode =
161100
/* Sienna Cichlid */
162101
static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] =
163102
{
164-
{
165-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
166-
.max_width = 4096,
167-
.max_height = 4096,
168-
.max_pixels_per_frame = 4096 * 4096,
169-
.max_level = 3,
170-
},
171-
{
172-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
173-
.max_width = 4096,
174-
.max_height = 4096,
175-
.max_pixels_per_frame = 4096 * 4096,
176-
.max_level = 5,
177-
},
178-
{
179-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
180-
.max_width = 4096,
181-
.max_height = 4096,
182-
.max_pixels_per_frame = 4096 * 4096,
183-
.max_level = 52,
184-
},
185-
{
186-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
187-
.max_width = 4096,
188-
.max_height = 4096,
189-
.max_pixels_per_frame = 4096 * 4096,
190-
.max_level = 4,
191-
},
192-
{
193-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
194-
.max_width = 8192,
195-
.max_height = 4352,
196-
.max_pixels_per_frame = 8192 * 4352,
197-
.max_level = 186,
198-
},
199-
{
200-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
201-
.max_width = 4096,
202-
.max_height = 4096,
203-
.max_pixels_per_frame = 4096 * 4096,
204-
.max_level = 0,
205-
},
206-
{
207-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
208-
.max_width = 8192,
209-
.max_height = 4352,
210-
.max_pixels_per_frame = 8192 * 4352,
211-
.max_level = 0,
212-
},
213-
{
214-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1,
215-
.max_width = 8192,
216-
.max_height = 4352,
217-
.max_pixels_per_frame = 8192 * 4352,
218-
.max_level = 0,
219-
},
103+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
104+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
105+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
106+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
107+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
108+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
109+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
110+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
220111
};
221112

222113
static const struct amdgpu_video_codecs sc_video_codecs_decode =
@@ -228,80 +119,20 @@ static const struct amdgpu_video_codecs sc_video_codecs_decode =
228119
/* SRIOV Sienna Cichlid, not const since data is controlled by host */
229120
static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =
230121
{
231-
{
232-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
233-
.max_width = 4096,
234-
.max_height = 2304,
235-
.max_pixels_per_frame = 4096 * 2304,
236-
.max_level = 0,
237-
},
238-
{
239-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
240-
.max_width = 4096,
241-
.max_height = 2304,
242-
.max_pixels_per_frame = 4096 * 2304,
243-
.max_level = 0,
244-
},
122+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
123+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
245124
};
246125

247126
static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] =
248127
{
249-
{
250-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
251-
.max_width = 4096,
252-
.max_height = 4096,
253-
.max_pixels_per_frame = 4096 * 4096,
254-
.max_level = 3,
255-
},
256-
{
257-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
258-
.max_width = 4096,
259-
.max_height = 4096,
260-
.max_pixels_per_frame = 4096 * 4096,
261-
.max_level = 5,
262-
},
263-
{
264-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
265-
.max_width = 4096,
266-
.max_height = 4096,
267-
.max_pixels_per_frame = 4096 * 4096,
268-
.max_level = 52,
269-
},
270-
{
271-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
272-
.max_width = 4096,
273-
.max_height = 4096,
274-
.max_pixels_per_frame = 4096 * 4096,
275-
.max_level = 4,
276-
},
277-
{
278-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
279-
.max_width = 8192,
280-
.max_height = 4352,
281-
.max_pixels_per_frame = 8192 * 4352,
282-
.max_level = 186,
283-
},
284-
{
285-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
286-
.max_width = 4096,
287-
.max_height = 4096,
288-
.max_pixels_per_frame = 4096 * 4096,
289-
.max_level = 0,
290-
},
291-
{
292-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
293-
.max_width = 8192,
294-
.max_height = 4352,
295-
.max_pixels_per_frame = 8192 * 4352,
296-
.max_level = 0,
297-
},
298-
{
299-
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1,
300-
.max_width = 8192,
301-
.max_height = 4352,
302-
.max_pixels_per_frame = 8192 * 4352,
303-
.max_level = 0,
304-
},
128+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
129+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
130+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
131+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
132+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
133+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
134+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
135+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
305136
};
306137

307138
static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =
@@ -333,6 +164,19 @@ static const struct amdgpu_video_codecs bg_video_codecs_encode = {
333164
.codec_array = NULL,
334165
};
335166

167+
/* Yellow Carp*/
168+
static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = {
169+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
170+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
171+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
172+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
173+
};
174+
175+
static const struct amdgpu_video_codecs yc_video_codecs_decode = {
176+
.codec_count = ARRAY_SIZE(yc_video_codecs_decode_array),
177+
.codec_array = yc_video_codecs_decode_array,
178+
};
179+
336180
static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
337181
const struct amdgpu_video_codecs **codecs)
338182
{
@@ -353,12 +197,17 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
353197
case CHIP_NAVY_FLOUNDER:
354198
case CHIP_DIMGREY_CAVEFISH:
355199
case CHIP_VANGOGH:
356-
case CHIP_YELLOW_CARP:
357200
if (encode)
358201
*codecs = &nv_video_codecs_encode;
359202
else
360203
*codecs = &sc_video_codecs_decode;
361204
return 0;
205+
case CHIP_YELLOW_CARP:
206+
if (encode)
207+
*codecs = &nv_video_codecs_encode;
208+
else
209+
*codecs = &yc_video_codecs_decode;
210+
return 0;
362211
case CHIP_BEIGE_GOBY:
363212
if (encode)
364213
*codecs = &bg_video_codecs_encode;
@@ -1387,7 +1236,10 @@ static int nv_common_early_init(void *handle)
13871236
AMD_PG_SUPPORT_VCN |
13881237
AMD_PG_SUPPORT_VCN_DPG |
13891238
AMD_PG_SUPPORT_JPEG;
1390-
adev->external_rev_id = adev->rev_id + 0x01;
1239+
if (adev->pdev->device == 0x1681)
1240+
adev->external_rev_id = adev->rev_id + 0x19;
1241+
else
1242+
adev->external_rev_id = adev->rev_id + 0x01;
13911243
break;
13921244
default:
13931245
/* FIXME: not supported yet */

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