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Merge tag 'cxl-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl
Pull CXL (Compute Express Link) updates from Dan Williams: - Fix detection of CXL host bridges to filter out disabled ACPI0016 devices in the ACPI DSDT. - Fix kernel lockdown integration to disable raw commands when raw PCI access is disabled. - Fix a broken debug message. - Add support for "Get Partition Info". I.e. enumerate the split between volatile and persistent capacity on bi-modal CXL memory expanders. - Re-factor the core by subject area. This is a work in progress. - Prepare libnvdimm to understand CXL labels in addition to EFI labels. This is a work in progress. * tag 'cxl-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl: (25 commits) cxl/registers: Fix Documentation warning cxl/pmem: Fix Documentation warning cxl/uapi: Fix defined but not used warnings cxl/pci: Fix debug message in cxl_probe_regs() cxl/pci: Fix lockdown level cxl/acpi: Do not add DSDT disabled ACPI0016 host bridge ports libnvdimm/labels: Add claim class helpers libnvdimm/labels: Add type-guid helpers libnvdimm/labels: Add blk special cases for nlabel and position helpers libnvdimm/labels: Add blk isetcookie set / validation helpers libnvdimm/labels: Add a checksum calculation helper libnvdimm/labels: Introduce label setter helpers libnvdimm/labels: Add isetcookie validation helper libnvdimm/labels: Introduce getters for namespace label fields cxl/mem: Adjust ram/pmem range to represent DPA ranges cxl/mem: Account for partitionable space in ram/pmem ranges cxl/pci: Store memory capacity values cxl/pci: Simplify register setup cxl/pci: Ignore unknown register block types cxl/core: Move memdev management to core ...
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Documentation/driver-api/cxl/memory-devices.rst

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,9 +36,15 @@ CXL Core
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.. kernel-doc:: drivers/cxl/cxl.h
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:internal:
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39-
.. kernel-doc:: drivers/cxl/core.c
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.. kernel-doc:: drivers/cxl/core/bus.c
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:doc: cxl core
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.. kernel-doc:: drivers/cxl/core/pmem.c
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:doc: cxl pmem
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.. kernel-doc:: drivers/cxl/core/regs.c
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:doc: cxl registers
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External Interfaces
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===================
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drivers/cxl/Makefile

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,9 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_CXL_BUS) += cxl_core.o
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obj-$(CONFIG_CXL_BUS) += core/
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obj-$(CONFIG_CXL_MEM) += cxl_pci.o
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obj-$(CONFIG_CXL_ACPI) += cxl_acpi.o
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obj-$(CONFIG_CXL_PMEM) += cxl_pmem.o
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7-
ccflags-y += -DDEFAULT_SYMBOL_NAMESPACE=CXL
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cxl_core-y := core.o
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cxl_pci-y := pci.o
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cxl_acpi-y := acpi.o
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cxl_pmem-y := pmem.o

drivers/cxl/acpi.c

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -243,6 +243,9 @@ static struct acpi_device *to_cxl_host_bridge(struct device *dev)
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{
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struct acpi_device *adev = to_acpi_device(dev);
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if (!acpi_pci_find_root(adev->handle))
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return NULL;
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if (strcmp(acpi_device_hid(adev), "ACPI0016") == 0)
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return adev;
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return NULL;
@@ -266,10 +269,6 @@ static int add_host_bridge_uport(struct device *match, void *arg)
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if (!bridge)
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return 0;
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pci_root = acpi_pci_find_root(bridge->handle);
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if (!pci_root)
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return -ENXIO;
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dport = find_dport_by_dev(root_port, match);
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if (!dport) {
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dev_dbg(host, "host bridge expected and not found\n");
@@ -282,6 +281,11 @@ static int add_host_bridge_uport(struct device *match, void *arg)
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return PTR_ERR(port);
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dev_dbg(host, "%s: add: %s\n", dev_name(match), dev_name(&port->dev));
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/*
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* Note that this lookup already succeeded in
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* to_cxl_host_bridge(), so no need to check for failure here
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*/
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pci_root = acpi_pci_find_root(bridge->handle);
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ctx = (struct cxl_walk_context){
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.dev = host,
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.root = pci_root->bus,

drivers/cxl/core/Makefile

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_CXL_BUS) += cxl_core.o
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ccflags-y += -DDEFAULT_SYMBOL_NAMESPACE=CXL -I$(srctree)/drivers/cxl
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cxl_core-y := bus.o
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cxl_core-y += pmem.o
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cxl_core-y += regs.o
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cxl_core-y += memdev.o

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