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Merge remote-tracking branch 'asoc/for-5.15' into asoc-linus
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‎Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt

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@@ -6,6 +6,7 @@ Required properties:
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"ti,da830-mcasp-audio" : for both DA830 & DA850 platforms
77
"ti,am33xx-mcasp-audio" : for AM33xx platforms (AM33xx, AM43xx, TI81xx)
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"ti,dra7-mcasp-audio" : for DRA7xx platforms
9+
"ti,omap4-mcasp-audio" : for OMAP4
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1011
- reg : Should contain reg specifiers for the entries in the reg-names property.
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- reg-names : Should contain:

‎Documentation/devicetree/bindings/sound/ics43432.txt

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Invensense ICS-43432 MEMS microphone with I2S output.
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Invensense ICS-43432-compatible MEMS microphone with I2S output.
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33
There are no software configuration options for this device, indeed, the only
44
host connection is the I2S interface. Apart from requirements on clock
@@ -8,7 +8,9 @@ contain audio data. A hardware pin determines if the device outputs data
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on the left or right channel of the I2S frame.
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1010
Required properties:
11-
- compatible : Must be "invensense,ics43432"
11+
- compatible: should be one of the following.
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"invensense,ics43432": For the Invensense ICS43432
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"cui,cmm-4030d-261": For the CUI CMM-4030D-261-I2S-TR
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Example:
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‎Documentation/devicetree/bindings/sound/mt8195-afe-pcm.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/mt8195-afe-pcm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek AFE PCM controller for mt8195
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maintainers:
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- Trevor Wu <trevor.wu@mediatek.com>
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properties:
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compatible:
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const: mediatek,mt8195-audio
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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mediatek,topckgen:
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$ref: "/schemas/types.yaml#/definitions/phandle"
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description: The phandle of the mediatek topckgen controller
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power-domains:
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maxItems: 1
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clocks:
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items:
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- description: 26M clock
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- description: audio pll1 clock
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- description: audio pll2 clock
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- description: clock divider for i2si1_mck
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- description: clock divider for i2si2_mck
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- description: clock divider for i2so1_mck
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- description: clock divider for i2so2_mck
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- description: clock divider for dptx_mck
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- description: a1sys hoping clock
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- description: audio intbus clock
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- description: audio hires clock
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- description: audio local bus clock
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- description: mux for dptx_mck
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- description: mux for i2so1_mck
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- description: mux for i2so2_mck
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- description: mux for i2si1_mck
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- description: mux for i2si2_mck
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- description: audio infra 26M clock
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- description: infra bus clock
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clock-names:
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items:
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- const: clk26m
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- const: apll1_ck
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- const: apll2_ck
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- const: apll12_div0
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- const: apll12_div1
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- const: apll12_div2
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- const: apll12_div3
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- const: apll12_div9
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- const: a1sys_hp_sel
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- const: aud_intbus_sel
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- const: audio_h_sel
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- const: audio_local_bus_sel
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- const: dptx_m_sel
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- const: i2so1_m_sel
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- const: i2so2_m_sel
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- const: i2si1_m_sel
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- const: i2si2_m_sel
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- const: infra_ao_audio_26m_b
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- const: scp_adsp_audiodsp
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mediatek,etdm-in1-chn-disabled:
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$ref: /schemas/types.yaml#/definitions/uint8-array
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maxItems: 24
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description: Specify which input channel should be disabled.
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mediatek,etdm-in2-chn-disabled:
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$ref: /schemas/types.yaml#/definitions/uint8-array
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maxItems: 16
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description: Specify which input channel should be disabled.
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patternProperties:
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"^mediatek,etdm-in[1-2]-mclk-always-on-rate-hz$":
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description: Specify etdm in mclk output rate for always on case.
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"^mediatek,etdm-out[1-3]-mclk-always-on-rate-hz$":
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description: Specify etdm out mclk output rate for always on case.
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"^mediatek,etdm-in[1-2]-multi-pin-mode$":
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type: boolean
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description: if present, the etdm data mode is I2S.
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"^mediatek,etdm-out[1-3]-multi-pin-mode$":
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type: boolean
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description: if present, the etdm data mode is I2S.
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"^mediatek,etdm-in[1-2]-cowork-source$":
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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etdm modules can share the same external clock pin. Specify
102+
which etdm clock source is required by this etdm in moudule.
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enum:
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- 0 # etdm1_in
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- 1 # etdm2_in
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- 2 # etdm1_out
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- 3 # etdm2_out
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"^mediatek,etdm-out[1-2]-cowork-source$":
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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etdm modules can share the same external clock pin. Specify
113+
which etdm clock source is required by this etdm out moudule.
114+
enum:
115+
- 0 # etdm1_in
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- 1 # etdm2_in
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- 2 # etdm1_out
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- 3 # etdm2_out
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required:
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- compatible
122+
- reg
123+
- interrupts
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- mediatek,topckgen
125+
- power-domains
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- clocks
127+
- clock-names
128+
129+
additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8195-clk.h>
134+
#include <dt-bindings/interrupt-controller/arm-gic.h>
135+
#include <dt-bindings/interrupt-controller/irq.h>
136+
#include <dt-bindings/power/mt8195-power.h>
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afe: mt8195-afe-pcm@10890000 {
139+
compatible = "mediatek,mt8195-audio";
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reg = <0x10890000 0x10000>;
141+
interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
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mediatek,topckgen = <&topckgen>;
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power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
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clocks = <&clk26m>,
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<&topckgen CLK_TOP_APLL1>,
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<&topckgen CLK_TOP_APLL2>,
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<&topckgen CLK_TOP_APLL12_DIV0>,
148+
<&topckgen CLK_TOP_APLL12_DIV1>,
149+
<&topckgen CLK_TOP_APLL12_DIV2>,
150+
<&topckgen CLK_TOP_APLL12_DIV3>,
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<&topckgen CLK_TOP_APLL12_DIV9>,
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<&topckgen CLK_TOP_A1SYS_HP_SEL>,
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<&topckgen CLK_TOP_AUD_INTBUS_SEL>,
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<&topckgen CLK_TOP_AUDIO_H_SEL>,
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<&topckgen CLK_TOP_AUDIO_LOCAL_BUS_SEL>,
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<&topckgen CLK_TOP_DPTX_M_SEL>,
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<&topckgen CLK_TOP_I2SO1_M_SEL>,
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<&topckgen CLK_TOP_I2SO2_M_SEL>,
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<&topckgen CLK_TOP_I2SI1_M_SEL>,
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<&topckgen CLK_TOP_I2SI2_M_SEL>,
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<&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>,
162+
<&scp_adsp CLK_SCP_ADSP_AUDIODSP>;
163+
clock-names = "clk26m",
164+
"apll1_ck",
165+
"apll2_ck",
166+
"apll12_div0",
167+
"apll12_div1",
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"apll12_div2",
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"apll12_div3",
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"apll12_div9",
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"a1sys_hp_sel",
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"aud_intbus_sel",
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"audio_h_sel",
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"audio_local_bus_sel",
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"dptx_m_sel",
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"i2so1_m_sel",
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"i2so2_m_sel",
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"i2si1_m_sel",
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"i2si2_m_sel",
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"infra_ao_audio_26m_b",
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"scp_adsp_audiodsp";
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};
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...

‎Documentation/devicetree/bindings/sound/mt8195-mt6359-rt1019-rt5682.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/mt8195-mt6359-rt1019-rt5682.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek MT8195 with MT6359, RT1019 and RT5682 ASoC sound card driver
8+
9+
maintainers:
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- Trevor Wu <trevor.wu@mediatek.com>
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description:
13+
This binding describes the MT8195 sound card.
14+
15+
properties:
16+
compatible:
17+
const: mediatek,mt8195_mt6359_rt1019_rt5682
18+
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mediatek,platform:
20+
$ref: "/schemas/types.yaml#/definitions/phandle"
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description: The phandle of MT8195 ASoC platform.
22+
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mediatek,dptx-codec:
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$ref: "/schemas/types.yaml#/definitions/phandle"
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description: The phandle of MT8195 Display Port Tx codec node.
26+
27+
mediatek,hdmi-codec:
28+
$ref: "/schemas/types.yaml#/definitions/phandle"
29+
description: The phandle of MT8195 HDMI codec node.
30+
31+
additionalProperties: false
32+
33+
required:
34+
- compatible
35+
- mediatek,platform
36+
37+
examples:
38+
- |
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40+
sound: mt8195-sound {
41+
compatible = "mediatek,mt8195_mt6359_rt1019_rt5682";
42+
mediatek,platform = <&afe>;
43+
pinctrl-names = "default";
44+
pinctrl-0 = <&aud_pins_default>;
45+
};
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...

‎Documentation/devicetree/bindings/sound/realtek,rt1015p.yaml

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properties:
1717
compatible:
18-
const: realtek,rt1015p
18+
enum:
19+
- realtek,rt1015p
20+
- realtek,rt1019p
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2022
sdb-gpios:
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description:

‎Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/renesas,rz-ssi.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Renesas RZ/G2L ASoC Sound Serial Interface (SSIF-2)
8+
9+
maintainers:
10+
- Biju Das <biju.das.jz@bp.renesas.com>
11+
12+
properties:
13+
compatible:
14+
items:
15+
- enum:
16+
- renesas,r9a07g044-ssi # RZ/G2{L,LC}
17+
- const: renesas,rz-ssi
18+
19+
reg:
20+
maxItems: 1
21+
22+
interrupts:
23+
maxItems: 4
24+
25+
interrupt-names:
26+
items:
27+
- const: int_req
28+
- const: dma_rx
29+
- const: dma_tx
30+
- const: dma_rt
31+
32+
clocks:
33+
maxItems: 4
34+
35+
clock-names:
36+
items:
37+
- const: ssi
38+
- const: ssi_sfr
39+
- const: audio_clk1
40+
- const: audio_clk2
41+
42+
power-domains:
43+
maxItems: 1
44+
45+
resets:
46+
maxItems: 1
47+
48+
dmas:
49+
minItems: 1
50+
maxItems: 2
51+
description:
52+
The first cell represents a phandle to dmac
53+
The second cell specifies the encoded MID/RID values of the SSI port
54+
connected to the DMA client and the slave channel configuration
55+
parameters.
56+
bits[0:9] - Specifies MID/RID value of a SSI channel as below
57+
MID/RID value of SSI rx0 = 0x256
58+
MID/RID value of SSI tx0 = 0x255
59+
MID/RID value of SSI rx1 = 0x25a
60+
MID/RID value of SSI tx1 = 0x259
61+
MID/RID value of SSI rt2 = 0x25f
62+
MID/RID value of SSI rx3 = 0x262
63+
MID/RID value of SSI tx3 = 0x261
64+
bit[10] - HIEN = 1, Detects a request in response to the rising edge
65+
of the signal
66+
bit[11] - LVL = 0, Detects based on the edge
67+
bits[12:14] - AM = 2, Bus cycle mode
68+
bit[15] - TM = 0, Single transfer mode
69+
70+
dma-names:
71+
oneOf:
72+
- items:
73+
- const: tx
74+
- const: rx
75+
- items:
76+
- const: rt
77+
78+
'#sound-dai-cells':
79+
const: 0
80+
81+
required:
82+
- compatible
83+
- reg
84+
- interrupts
85+
- interrupt-names
86+
- clocks
87+
- clock-names
88+
- resets
89+
- '#sound-dai-cells'
90+
91+
additionalProperties: false
92+
93+
examples:
94+
- |
95+
#include <dt-bindings/interrupt-controller/arm-gic.h>
96+
#include <dt-bindings/clock/r9a07g044-cpg.h>
97+
98+
ssi0: ssi@10049c00 {
99+
compatible = "renesas,r9a07g044-ssi",
100+
"renesas,rz-ssi";
101+
reg = <0x10049c00 0x400>;
102+
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
103+
<GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
104+
<GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
105+
<GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
106+
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
107+
clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
108+
<&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
109+
<&audio_clk1>,
110+
<&audio_clk2>;
111+
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
112+
power-domains = <&cpg>;
113+
resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
114+
dmas = <&dmac 0x2655>,
115+
<&dmac 0x2656>;
116+
dma-names = "tx", "rx";
117+
#sound-dai-cells = <0>;
118+
};

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