diff --git a/CMakeLists.txt b/CMakeLists.txt
index 5273d7b6..a471af54 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -25,7 +25,7 @@ if(MSVC)
     add_compile_options("/wd4324")
 endif()
 
-project(astcencoder VERSION 5.2.0)
+project(astcencoder VERSION 5.3.0)
 
 set(CMAKE_CXX_STANDARD 14)
 set(CMAKE_CXX_STANDARD_REQUIRED ON)
diff --git a/Docs/ChangeLog-5x.md b/Docs/ChangeLog-5x.md
index b17192d6..7dda5d5a 100644
--- a/Docs/ChangeLog-5x.md
+++ b/Docs/ChangeLog-5x.md
@@ -6,6 +6,22 @@ release of the 5.x series.
 All performance data on this page is measured on an Intel Core i5-9600K
 clocked at 4.2 GHz, running `astcenc` using AVX2 and 6 threads.
 
+<!-- ---------------------------------------------------------------------- -->
+## 5.3.0
+
+**Status:** March 2025
+
+The 5.3.0 release is a minor maintenance release.
+
+* **General:**
+  * **Feature:** Reference C builds (`ASTCENC_ISA_NONE`) now support compiling
+    for big-endian CPUs. Compile with `-DASTCENC_BIG_ENDIAN=ON` when compiling
+    for a big-endian target; it is not auto-detected.
+  * **Bug fix:** Builds using MSVC `cl.exe` that do not specify an explicit
+    ISA using the preprocessor configuration defines will now correctly
+    default to the SSE2 backend on x86-64 and the NEON backend on Arm64. Previously they would have defaulted to the reference C implementation,
+    which is around 3.25 times slower.
+
 <!-- ---------------------------------------------------------------------- -->
 ## 5.2.0