Missing `jalr` Instruction Format

[Wladefant]

Hello and thank you. I am coming from the risc-v vscode extension that uses this simulator https://github.com/hm-riscv/vscode-riscv-venus

Environment

• Extension/Venus Simulator Version: 1.7.0
• Operating System: Windows 11
• ISA Reference: RISC-V Unprivileged ISA V20191213

Issue Description

When using the VSCode extension based on the Venus simulator, an AssemblerError is thrown for using the jalr instruction in a displaced notation format.

Error Message

AssemblerError: fix.S:39: I-Type Instructions should not be in Displaced Notation! jalr zero, 0(ra)

This error appears inconsistent with the GNU Assembler's acceptance of both jalr zero,ra,0 and jalr zero,0(ra) syntax, as indicated in the ISA documentation and the GNU Assembler source code (https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=opcodes/riscv-opc.c;h=fcba49972f01b639072d303ace0804c900c12bfb;hb=refs/heads/master#l370).

Expected Behavior

Both jalr zero,ra,0 and jalr zero,0(ra) should be accepted by the assembler without errors, following the GNU Assembler's example and the written rule in the RISC-V ISA documentation.

Steps to Reproduce

1. Write a RISC-V assembly program using the jalr instruction in the format jalr zero, 0(ra).
2. Attempt to assemble the program using the VSCode extension for RISC-V based on the Venus simulator.
3. Observe the AssemblerError indicating that the displaced notation should not be used.

Additional Context

Attached is an excerpt from the RISC-V ISA documentation indicating the standard jalr instruction usage, which seems to align with the GNU Assembler's flexibility. This discrepancy between the ISA and the Venus simulator's interpretation could lead to confusion and potential errors in assembly programs.